[coreboot] Rangeley reset

Wen Wang wen.wang at adiengineering.com
Tue Aug 26 22:09:22 CEST 2014


Has anybody tested reset signal (PMU_RESETBUTTON_B) on Rangeley/Avoton? The
board seems to shut down after asserting the signal (pushing the reset
button). I turn on an LED in early_mainboard_romstage_entry(). The LED was
not on indicating the function was not executed. Below is what printed out
on console after reset:

coreboot-0f49404 Tue Aug 26 15:28:40 EDT 2014 starting...
POST: 0x41
POST: 0x42
Setting up static southbridge registers... done.
Disabling Watchdog timer... done.
RTC Init
POST: 0x46
POST: 0x47
Starting the Intel FSP (early_init)
Configure Default UPD Data
PcdEnableIQAT 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableUsb20 1
PcdEnableSata2 1
PcdEnableSata3 1
find_current_mrc_cache_local: No valid fast boot cache found.
FSP MRC cache not present.

For cold boot, it will continue to spit out boot messages.


-- Wen Wang

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