[coreboot] ASUS A8V-E Deluxe RAM initialization issues AND dual-core success story

Michael Büchler mbuechler.3 at gmail.com
Sun Oct 27 18:03:49 CET 2013


On Sun, 2013-10-27 at 00:14 +0200, Rudolf Marek wrote:
> > Anything I can do to debug? Do you have an idea?
> 
> Yes it looks like memory is setup in wrong way. I did the port for ASUS A8V-E SE 
> board. Possible reasons:
> 
> 0) something is wrong with placement of dimms
> 
> I remember sometimes memory did not work well if in second channel, sometimes 
> even the board had it labeled vice versa... Try to put dimm in different slot. 
> It could fix single dimm issues

You're right with the single dimm issues, I have to use slot B1 or B2
for a single module, vendor BIOS and coreboot. But I also found a more
or less working configuration I had somehow missed before: putting both
1GB ECC modules in B1 and B2 makes coreboot detect full 2GB and boot,
but with reduced speed: "Memory speed reduced due to signal loading
conditions", and not DualChannel of course; see log. Anything else hangs
at "Jumping to image" or detects only 1GB.

> 1) something is wrong with dualchannel setup
> 
> This is usually sign that the following table is wrong:
> 
> You can try to modify it like this as it is on A8V-E SE because the deluxe 
> version seems wrong to me (you have only 4 dimm slots)
> 
>          static const uint16_t spd_addr[] = {
>                  // Node 0
>                  DIMM0, DIMM2, 0, 0,
>                  0, 0, 0, 0,
>                  // Node 1
>                  DIMM1, DIMM3, 0, 0,
>                  0, 0, 0, 0,
>          };

I used i2cdetect like you suggested (which was interesting!) and I found
out that this should be the correct table. The labels on the board seem
to be vice versa indeed:

Board label: A1 | A2 | B1 | B2  <-- physical layout
             -----------------
i2c address: 51 | 53 | 50 | 52

With both modules in A1/B1 or A2/B2 the system would boot now, but only
1GB was detected, or 512MB with 512MB modules, also with non-ECC!
With both modules in B1/B2 it was the same as before (2GB detected,
reduced speed, but works).
Both log files are with this corrected table.

I also tried to swap DIMM0, DIMM2 with DIMM1, DIMM3 and the results from
i2cdetect were funny:

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- -- -- -- -- -- -- -- -- 
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2f 
30: -- -- -- -- -- 35 36 37 38 39 3a 3b 3c 3d 3e 3f 
40: 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 
50: 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 
60: 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 
70: 70 71 72 73 74 75 76 77

Also, only the module in B1 was detected, not in B2, if I remember
correctly..

> 2) something is wrong with memory init
> 
> lets wait if above helps, I suspect it should.

I'm not sure right now if it did.. the table is probably correct but now
even non-ECC is not fully detected. Assuming it IS correct, is there
anything I can try except making myself familiar with RAM init and
searching for a bug, which could take a while, like, forever?

> > Apart from that I got a little success story: the VIA K8T890 chipset on
> > this mainboard had a bug in it's first revision, making it incompatible
> > with dual-core CPUs. I was curious if coreboot also had this limitation,
> > so I bought a cheap dual-core Opteron 180 and tested it. Vendor BIOS:
> > one core detected in linux. coreboot: two cores!!
> 
> Yes because I was not aware of this problem while implementing this chipset 
> support 6? years ago. Do you have any details?

I'm glad you were not! I don't know any more than what I found using
google though [1]. The  A8V-E SE had a newer chipset revision which was
fixed. Probably they shipped some A8V-E Deluxe boards with the new
revision and mine already has it as well.

Thank you for your help Rudolf!

Michael
-------------- next part --------------


coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 starting...
now booting... romstage


coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 starting...
now booting... real_main
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started: 
now booting... Core0 started
started ap apicid: * AP 01started

SBLink=00
NC node|link=00
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x6e, unfiltered freq_cap=0x75
pos=0x6e, filtered freq_cap=0x75
freq_cap1=0x75, freq_cap2=0x75
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
ht reset -
soft r

coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 starting...
now booting... romstage


coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 starting...
now booting... real_main
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started: 
now booting... Core0 started
started ap apicid: * AP 01started

SBLink=00
NC node|link=00
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x6e, unfiltered freq_cap=0x75
pos=0x6e, filtered freq_cap=0x75
freq_cap1=0x75, freq_cap2=0x75
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
Current fid_cur: 0x10, fid_max: 0x10
Requested fid_new: 0x10
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
Device error
Registered
Setting DualDIMMen
200MHz
Interleaved
RAM end at 0x00100000 kB
Lower RAM end at 0x00100000 kB
Ram3
ECC enabled
Initializing memory:  done
Ram4
v_esp=000cff08
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now 
Clearing initial memory region: Done
Loading image.
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffc00/0x80000
CBFS: CBFS location: 0x0~0x7fc20, align: 64
CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0.
CBFS:  - load entry 0x0 file name (16 bytes)...
CBFS:  (unmatched file @0x0: cmos_layout.bin)
CBFS:  - load entry 0x740 file name (32 bytes)...
CBFS:  (unmatched file @0x740: fallback/romstage)
CBFS:  - load entry 0xb240 file name (32 bytes)...
CBFS: Found file (offset=0xb278, len=60420).
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (516152 bytes), entry @ 0x100000
CBFS: stage loaded.
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 booting...
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:0f.1: enabled 1
PCI: 00:11.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PNP: 002e.0: enabled 1
-------------- next part --------------


coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 starting...
now booting... romstage


coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 starting...
now booting... real_main
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started: 
now booting... Core0 started
started ap apicid: * AP 01started

SBLink=00
NC node|link=00
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x6e, unfiltered freq_cap=0x75
pos=0x6e, filtered freq_cap=0x75
freq_cap1=0x75, freq_cap2=0x75
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
ht reset -
soft r

coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 starting...
now booting... romstage


coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 starting...
now booting... real_main
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started: 
now booting... Core0 started
started ap apicid: * AP 01started

SBLink=00
NC node|link=00
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x6e, unfiltered freq_cap=0x75
pos=0x6e, filtered freq_cap=0x75
freq_cap1=0x75, freq_cap2=0x75
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
Current fid_cur: 0x10, fid_max: 0x10
Requested fid_new: 0x10
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
Registered
Setting DualDIMMen
Memory speed reduced due to signal loading conditions
166MHz
Interleaved
RAM end at 0x00200000 kB
Lower RAM end at 0x00200000 kB
Ram3
ECC enabled
Initializing memory:  done
Ram4
v_esp=000cff08
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now 
Clearing initial memory region: Done
Loading image.
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffc00/0x80000
CBFS: CBFS location: 0x0~0x7fc20, align: 64
CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0.
CBFS:  - load entry 0x0 file name (16 bytes)...
CBFS:  (unmatched file @0x0: cmos_layout.bin)
CBFS:  - load entry 0x740 file name (32 bytes)...
CBFS:  (unmatched file @0x740: fallback/romstage)
CBFS:  - load entry 0xb240 file name (32 bytes)...
CBFS: Found file (offset=0xb278, len=60420).
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (516152 bytes), entry @ 0x100000
CBFS: stage loaded.
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-4.0-4742-g553fe1c-dirty Sun Oct 27 12:15:38 CET 2013 booting...
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:0f.1: enabled 1
PCI: 00:11.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PNP: 002e.0: enabled 1


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