[coreboot] Asrock IMB-A180 not booting
Prop 395
prop395 at gmail.com
Mon Nov 25 17:42:12 CET 2013
On 11/22/2013 03:22 PM, Aaron Durbin wrote:
> On Fri, Nov 22, 2013 at 1:09 PM, Prop 395 <prop395 at gmail.com> wrote:
>> When I try coreboot/SeaBIOS on the Asrock IMB-A180 I cannot get it boot up.
>> I have looked at the debug log and have not seen any obvious issues.
>> Display remains off and USB keyboard/mouse inactive.
>>
>> Any help greatly appreciated!
>>
>> Debug log:
>> USB
>> coreboot-4.0-4781-gfe6bdd9 Thu Nov 21 17:38:55 PST 2013 booting...
>> BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
>> BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 0 exit 0
>> Enumerating buses...
>> Show all devs...Before device enumeration.
>> Root Device: enabled 1
>> CPU_CLUSTER: 0: enabled 1
>> APIC: 00: enabled 1
>> DOMAIN: 0000: enabled 1
>> PCI: 00:00.0: enabled 1
>> PCI: 00:01.0: enabled 1
>> PCI: 00:01.1: enabled 1
>> PCI: 00:02.0: enabled 1
>> PCI: 00:02.1: enabled 1
>> PCI: 00:02.2: enabled 1
>> PCI: 00:02.3: enabled 1
>> PCI: 00:02.4: enabled 1
>> PCI: 00:02.5: enabled 1
>> PCI: 00:10.0: enabled 1
>> PCI: 00:11.0: enabled 1
>> PCI: 00:12.0: enabled 1
>> PCI: 00:12.2: enabled 1
>> PCI: 00:13.0: enabled 1
>> PCI: 00:13.2: enabled 1
>> PCI: 00:14.0: enabled 1
>> I2C: 00:50: enabled 1
>> I2C: 00:51: enabled 1
>> PCI: 00:14.2: enabled 1
>> PCI: 00:14.3: enabled 1
>> PCI: 00:14.7: enabled 1
>> PCI: 00:18.0: enabled 1
>> PCI: 00:18.1: enabled 1
>> PCI: 00:18.2: enabled 1
>> PCI: 00:18.3: enabled 1
>> PCI: 00:18.4: enabled 1
>> PCI: 00:18.5: enabled 1
>> Compare with tree...
>> Root Device: enabled 1
>> CPU_CLUSTER: 0: enabled 1
>> APIC: 00: enabled 1
>> DOMAIN: 0000: enabled 1
>> PCI: 00:00.0: enabled 1
>> PCI: 00:01.0: enabled 1
>> PCI: 00:01.1: enabled 1
>> PCI: 00:02.0: enabled 1
>> PCI: 00:02.1: enabled 1
>> PCI: 00:02.2: enabled 1
>> PCI: 00:02.3: enabled 1
>> PCI: 00:02.4: enabled 1
>> PCI: 00:02.5: enabled 1
>> PCI: 00:10.0: enabled 1
>> PCI: 00:11.0: enabled 1
>> PCI: 00:12.0: enabled 1
>> PCI: 00:12.2: enabled 1
>> PCI: 00:13.0: enabled 1
>> PCI: 00:13.2: enabled 1
>> PCI: 00:14.0: enabled 1
>> I2C: 00:50: enabled 1
>> I2C: 00:51: enabled 1
>> PCI: 00:14.2: enabled 1
>> PCI: 00:14.3: enabled 1
>> PCI: 00:14.7: enabled 1
>> PCI: 00:18.0: enabled 1
>> PCI: 00:18.1: enabled 1
>> PCI: 00:18.2: enabled 1
>> PCI: 00:18.3: enabled 1
>> PCI: 00:18.4: enabled 1
>> PCI: 00:18.5: enabled 1
>> Mainboard IMB-A180 Enable.
>> scan_static_bus for Root Device
>> setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000
>> setup_bsp_ramtop, TOP MEM2: msr.lo = 0x20000000, msr.hi = 0x00000001
>> setup_uma_memory: uma size 0x20000000, memory start 0xc0000000
>> CPU_CLUSTER: 0 enabled
>> DOMAIN: 0000 enabled
>> CPU_CLUSTER: 0 scanning...
>> PCI: 00:18.5 family16h, core_max=0x8, core_nums=0x7, siblings=0x1
>> node 0x0 core 0x0 apicid=0x0
>> CPU: APIC: 00 enabled
>> node 0x0 core 0x1 apicid=0x1
>> CPU: APIC: 01 enabled
>> DOMAIN: 0000 scanning...
>> PCI: pci_scan_bus for bus 00
>> PCI: 00:00.0 [1022/1536] ops
>> PCI: 00:00.0 [1022/1536] enabled
>> PCI: 00:01.0 [1002/9834] enabled
>> PCI: 00:01.1 [1002/9840] enabled
>> PCI: 00:02.0 [1022/1538] enabled
>> PCI: Static device PCI: 00:02.1 not found, disabling it.
>> PCI: Static device PCI: 00:02.2 not found, disabling it.
>> Capability: type 0x01 @ 0x50
>> Capability: type 0x10 @ 0x58
>> Capability: type 0x05 @ 0xa0
>> Capability: type 0x0d @ 0xb0
>> Capability: type 0x08 @ 0xb8
>> Capability: type 0x01 @ 0x50
>> Capability: type 0x10 @ 0x58
>> PCI: 00:02.3 subordinate bus PCI Express
>> PCI: 00:02.3 [1022/1439] enabled
>> Capability: type 0x01 @ 0x50
>> Capability: type 0x10 @ 0x58
>> Capability: type 0x05 @ 0xa0
>> Capability: type 0x0d @ 0xb0
>> Capability: type 0x08 @ 0xb8
>> Capability: type 0x01 @ 0x50
>> Capability: type 0x10 @ 0x58
>> PCI: 00:02.4 subordinate bus PCI Express
>> PCI: 00:02.4 [1022/1439] enabled
>> PCI: Static device PCI: 00:02.5 not found, disabling it.
>> hudson_enable()
>> PCI: 00:10.0 [1022/7814] enabled
>> hudson_enable()
>> PCI: 00:11.0 [1022/7801] ops
>> PCI: 00:11.0 [1022/7801] enabled
>> hudson_enable()
>> PCI: 00:12.0 [1022/7807] ops
>> PCI: 00:12.0 [1022/7807] enabled
>> hudson_enable()
>> PCI: 00:12.2 [1022/7808] ops
>> PCI: 00:12.2 [1022/7808] enabled
>> hudson_enable()
>> PCI: 00:13.0 [1022/7807] ops
>> PCI: 00:13.0 [1022/7807] enabled
>> hudson_enable()
>> PCI: 00:13.2 [1022/7808] ops
>> PCI: 00:13.2 [1022/7808] enabled
>> hudson_enable()
>> PCI: 00:14.0 [1022/780b] bus ops
>> PCI: 00:14.0 [1022/780b] enabled
>> hudson_enable()
>> PCI: 00:14.2 [1022/780d] ops
>> PCI: 00:14.2 [1022/780d] enabled
>> hudson_enable()
>> PCI: 00:14.3 [1022/780e] bus ops
>> PCI: 00:14.3 [1022/780e] enabled
>> hudson_enable()
>> PCI: 00:14.7 [1022/7813] ops
>> PCI: 00:14.7 [1022/7813] enabled
>> PCI: 00:16.0 [1022/7807] ops
>> PCI: 00:16.0 [1022/7807] enabled
>> PCI: 00:16.2 [1022/7808] ops
>> PCI: 00:16.2 [1022/7808] enabled
>> PCI: 00:18.0 [1022/1530] enabled
>> PCI: 00:18.1 [1022/1531] enabled
>> PCI: 00:18.2 [1022/1532] enabled
>> PCI: 00:18.3 [1022/1533] enabled
>> PCI: 00:18.4 [1022/1534] enabled
>> PCI: 00:18.5 [1022/1535] enabled
>> do_pci_scan_bridge for PCI: 00:02.3
>> PCI: pci_scan_bus for bus 01
>> PCI: 01:00.0 [10ec/8168] enabled
>> PCI: 01:00.1 [10ec/816a] enabled
>> PCI: 01:00.2 [10ec/816b] enabled
>> PCI: 01:00.3 [10ec/816c] enabled
>> PCI: pci_scan_bus returning with max=001
>> Capability: type 0x01 @ 0x40
>> Capability: type 0x05 @ 0x50
>> Capability: type 0x10 @ 0x70
>> Capability: type 0x01 @ 0x50
>> Capability: type 0x10 @ 0x58
>> Capability: type 0x01 @ 0x40
>> Capability: type 0x05 @ 0x50
>> Capability: type 0x10 @ 0x70
>> Capability: type 0x01 @ 0x50
>> Capability: type 0x10 @ 0x58
>> Capability: type 0x01 @ 0x40
>> Capability: type 0x05 @ 0x50
>> Capability: type 0x10 @ 0x70
>> Capability: type 0x01 @ 0x50
>> Capability: type 0x10 @ 0x58
>> Capability: type 0x01 @ 0x40
>> Capability: type 0x05 @ 0x50
>> Capability: type 0x10 @ 0x70
>> Capability: type 0x01 @ 0x50
>> Capability: type 0x10 @ 0x58
>> do_pci_scan_bridge returns max 1
>> do_pci_scan_bridge for PCI: 00:02.4
>> PCI: pci_scan_bus for bus 02
>> PCI: 02:00.0 [10ec/8168] enabled
>> PCI: pci_scan_bus returning with max=002
>> Capability: type 0x01 @ 0x40
>> Capability: type 0x05 @ 0x50
>> Capability: type 0x10 @ 0x70
>> Capability: type 0x01 @ 0x50
>> Capability: type 0x10 @ 0x58
>> do_pci_scan_bridge returns max 2
>> scan_static_bus for PCI: 00:14.0
>> smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
>> smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
>> scan_static_bus for PCI: 00:14.0 done
>> scan_static_bus for PCI: 00:14.3
>> scan_static_bus for PCI: 00:14.3 done
>> PCI: pci_scan_bus returning with max=002
>> scan_static_bus for Root Device done
>> done
>> BS: BS_DEV_ENUMERATE times (us): entry 0 run 284656 exit 0
>> found VGA at PCI: 00:01.0
>> Setting up VGA for PCI: 00:01.0
>> Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
>> Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
>> Allocating resources...
>> Reading resources...
>> Root Device read_resources bus 0 link: 0
>> CPU_CLUSTER: 0 read_resources bus 0 link: 0
>> APIC: 00 missing read_resources
>> APIC: 01 missing read_resources
>> CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
>> fx_devs=0x1
>> DOMAIN: 0000 read_resources bus 0 link: 0
>> PCI: 00:02.3 read_resources bus 1 link: 0
>> PCI: 00:02.3 read_resources bus 1 link: 0 done
>> PCI: 00:02.4 read_resources bus 2 link: 0
>> PCI: 00:02.4 read_resources bus 2 link: 0 done
>> More than one caller of pci_ehci_read_resources from PCI: 00:12.0
>> PCI: 00:12.2 EHCI BAR hook registered
>> More than one caller of pci_ehci_read_resources from PCI: 00:13.0
>> More than one caller of pci_ehci_read_resources from PCI: 00:13.2
>> PCI: 00:14.0 read_resources bus 1 link: 0
>> I2C: 01:50 missing read_resources
>> I2C: 01:51 missing read_resources
>> PCI: 00:14.0 read_resources bus 1 link: 0 done
>> More than one caller of pci_ehci_read_resources from PCI: 00:16.0
>> More than one caller of pci_ehci_read_resources from PCI: 00:16.2
>> PCI: 00:18.0 read_resources bus 0 link: 0
>> PCI: 00:18.0 read_resources bus 0 link: 0 done
>> PCI: 00:18.0 read_resources bus 0 link: 1
>> PCI: 00:18.0 read_resources bus 0 link: 1 done
>> PCI: 00:18.0 read_resources bus 0 link: 2
>> PCI: 00:18.0 read_resources bus 0 link: 2 done
>> PCI: 00:18.0 read_resources bus 0 link: 3
>> PCI: 00:18.0 read_resources bus 0 link: 3 done
>> DOMAIN: 0000 read_resources bus 0 link: 0 done
>> Root Device read_resources bus 0 link: 0 done
>> Done reading resources.
>> Show resources in subtree (Root Device)...After reading.
>> Root Device child on link 0 CPU_CLUSTER: 0
>> CPU_CLUSTER: 0 child on link 0 APIC: 00
>> CPU_CLUSTER: 0 resource base a0000000 size 10000000 align 0 gran 0 limit 0
>> flags f0000200 index c0010058
>> APIC: 00
>> APIC: 01
>> DOMAIN: 0000 child on link 0 PCI: 00:00.0
>> DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags
>> 40040100 index 10000000
>> DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags
>> 40040200 index 10000100
>> PCI: 00:00.0
>> PCI: 00:01.0
>> PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit
>> ffffffffffffffff flags 1201 index 10
>> PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit
>> ffffffffffffffff flags 1201 index 18
>> PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100
>> index 20
>> PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff
>> flags 200 index 24
>> PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff
>> flags 2200 index 30
>> PCI: 00:01.1
>> PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit
>> ffffffffffffffff flags 201 index 10
>> PCI: 00:02.0
>> PCI: 00:02.1
>> PCI: 00:02.2
>> PCI: 00:02.3 child on link 0 PCI: 01:00.0
>> PCI: 00:02.3 resource base 0 size 0 align 12 gran 12 limit ffffffff flags
>> 80102 index 1c
>> PCI: 00:02.3 resource base 0 size 0 align 20 gran 20 limit
>> ffffffffffffffff flags 81202 index 24
>> PCI: 00:02.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
>> 80202 index 20
>> PCI: 01:00.0
>> PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags
>> 100 index 10
>> PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit
>> ffffffffffffffff flags 201 index 18
>> PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit
>> ffffffffffffffff flags 1201 index 20
>> PCI: 01:00.1
>> PCI: 01:00.1 resource base 0 size 100 align 8 gran 8 limit ffff flags
>> 100 index 10
>> PCI: 01:00.1 resource base 0 size 1000 align 12 gran 12 limit
>> ffffffffffffffff flags 201 index 18
>> PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit
>> ffffffffffffffff flags 201 index 20
>> PCI: 01:00.2
>> PCI: 01:00.2 resource base 0 size 100 align 8 gran 8 limit ffff flags
>> 100 index 10
>> PCI: 01:00.2 resource base 0 size 1000 align 12 gran 12 limit
>> ffffffffffffffff flags 201 index 18
>> PCI: 01:00.2 resource base 0 size 4000 align 14 gran 14 limit
>> ffffffffffffffff flags 201 index 20
>> PCI: 01:00.3
>> PCI: 01:00.3 resource base 0 size 100 align 8 gran 8 limit ffff flags
>> 100 index 10
>> PCI: 01:00.3 resource base 0 size 100 align 8 gran 8 limit
>> ffffffffffffffff flags 201 index 18
>> PCI: 01:00.3 resource base 0 size 4000 align 14 gran 14 limit
>> ffffffffffffffff flags 201 index 20
>> PCI: 00:02.4 child on link 0 PCI: 02:00.0
>> PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags
>> 80102 index 1c
>> PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit
>> ffffffffffffffff flags 81202 index 24
>> PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
>> 80202 index 20
>> PCI: 02:00.0
>> PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags
>> 100 index 10
>> PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit
>> ffffffffffffffff flags 1201 index 18
>> PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit
>> ffffffffffffffff flags 1201 index 20
>> PCI: 00:02.5
>> PCI: 00:10.0
>> PCI: 00:10.0 resource base 0 size 2000 align 13 gran 13 limit
>> ffffffffffffffff flags 201 index 10
>> PCI: 00:11.0
>> PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
>> index 10
>> PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
>> index 14
>> PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
>> index 18
>> PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
>> index 1c
>> PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100
>> index 20
>> PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff
>> flags 200 index 24
>> PCI: 00:12.0
>> PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
>> flags 200 index 10
>> PCI: 00:12.2
>> PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
>> 200 index 10
>> PCI: 00:13.0
>> PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
>> flags 200 index 10
>> PCI: 00:13.2
>> PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
>> 200 index 10
>> PCI: 00:14.0 child on link 0 I2C: 01:50
>> I2C: 01:50
>> I2C: 01:51
>> PCI: 00:14.2
>> PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit
>> ffffffffffffffff flags 201 index 10
>> PCI: 00:14.3
>> PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffcf flags
>> 200 index a0
>> PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
>> c0040100 index 10000000
>> PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
>> flags c0040200 index 10000100
>> PCI: 00:14.7
>> PCI: 00:14.7 resource base 0 size 100 align 8 gran 8 limit
>> ffffffffffffffff flags 201 index 10
>> PCI: 00:16.0
>> PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
>> flags 200 index 10
>> PCI: 00:16.2
>> PCI: 00:16.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
>> 200 index 10
>> PCI: 00:18.0
>> PCI: 00:18.1
>> PCI: 00:18.2
>> PCI: 00:18.3
>> PCI: 00:18.4
>> PCI: 00:18.5
>> DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit:
>> ffff
>> PCI: 00:02.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
>> ffffffff
>> PCI: 01:00.0 10 * [0x0 - 0xff] io
>> PCI: 01:00.1 10 * [0x400 - 0x4ff] io
>> PCI: 01:00.2 10 * [0x800 - 0x8ff] io
>> PCI: 01:00.3 10 * [0xc00 - 0xcff] io
>> PCI: 00:02.3 compute_resources_io: base: d00 size: 1000 align: 12 gran: 12
>> limit: ffff done
>> PCI: 00:02.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
>> ffffffff
>> PCI: 02:00.0 10 * [0x0 - 0xff] io
>> PCI: 00:02.4 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12
>> limit: ffff done
>> PCI: 00:02.3 1c * [0x0 - 0xfff] io
>> PCI: 00:02.4 1c * [0x1000 - 0x1fff] io
>> PCI: 00:01.0 20 * [0x2000 - 0x20ff] io
>> PCI: 00:11.0 20 * [0x2400 - 0x240f] io
>> PCI: 00:11.0 10 * [0x2410 - 0x2417] io
>> PCI: 00:11.0 18 * [0x2418 - 0x241f] io
>> PCI: 00:11.0 14 * [0x2420 - 0x2423] io
>> PCI: 00:11.0 1c * [0x2424 - 0x2427] io
>> DOMAIN: 0000 compute_resources_io: base: 2428 size: 2428 align: 12 gran: 0
>> limit: ffff done
>> DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:
>> ffffffff
>> PCI: 00:02.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
>> limit: ffffffffffffffff
>> PCI: 01:00.0 20 * [0x0 - 0x3fff] prefmem
>> PCI: 00:02.3 compute_resources_prefmem: base: 4000 size: 100000 align: 20
>> gran: 20 limit: ffffffffffffffff done
>> PCI: 00:02.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
>> limit: ffffffff
>> PCI: 01:00.1 20 * [0x0 - 0x3fff] mem
>> PCI: 01:00.2 20 * [0x4000 - 0x7fff] mem
>> PCI: 01:00.3 20 * [0x8000 - 0xbfff] mem
>> PCI: 01:00.0 18 * [0xc000 - 0xcfff] mem
>> PCI: 01:00.1 18 * [0xd000 - 0xdfff] mem
>> PCI: 01:00.2 18 * [0xe000 - 0xefff] mem
>> PCI: 01:00.3 18 * [0xf000 - 0xf0ff] mem
>> PCI: 00:02.3 compute_resources_mem: base: f100 size: 100000 align: 20 gran:
>> 20 limit: ffffffff done
>> PCI: 00:02.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
>> limit: ffffffffffffffff
>> PCI: 02:00.0 20 * [0x0 - 0x3fff] prefmem
>> PCI: 02:00.0 18 * [0x4000 - 0x4fff] prefmem
>> PCI: 00:02.4 compute_resources_prefmem: base: 5000 size: 100000 align: 20
>> gran: 20 limit: ffffffffffffffff done
>> PCI: 00:02.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
>> limit: ffffffff
>> PCI: 00:02.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
>> limit: ffffffff done
>> PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem
>> PCI: 00:01.0 18 * [0x10000000 - 0x107fffff] prefmem
>> PCI: 00:02.3 24 * [0x10800000 - 0x108fffff] prefmem
>> PCI: 00:02.3 20 * [0x10900000 - 0x109fffff] mem
>> PCI: 00:02.4 24 * [0x10a00000 - 0x10afffff] prefmem
>> PCI: 00:01.0 24 * [0x10b00000 - 0x10b3ffff] mem
>> PCI: 00:01.0 30 * [0x10b40000 - 0x10b5ffff] mem
>> PCI: 00:01.1 10 * [0x10b60000 - 0x10b63fff] mem
>> PCI: 00:14.2 10 * [0x10b64000 - 0x10b67fff] mem
>> PCI: 00:10.0 10 * [0x10b68000 - 0x10b69fff] mem
>> PCI: 00:12.0 10 * [0x10b6a000 - 0x10b6afff] mem
>> PCI: 00:13.0 10 * [0x10b6b000 - 0x10b6bfff] mem
>> PCI: 00:16.0 10 * [0x10b6c000 - 0x10b6cfff] mem
>> PCI: 00:11.0 24 * [0x10b6d000 - 0x10b6d3ff] mem
>> PCI: 00:12.2 10 * [0x10b6d400 - 0x10b6d4ff] mem
>> PCI: 00:13.2 10 * [0x10b6d500 - 0x10b6d5ff] mem
>> PCI: 00:14.7 10 * [0x10b6d600 - 0x10b6d6ff] mem
>> PCI: 00:16.2 10 * [0x10b6d700 - 0x10b6d7ff] mem
>> PCI: 00:14.3 a0 * [0x10b6d800 - 0x10b6d800] mem
>> DOMAIN: 0000 compute_resources_mem: base: 10b6d801 size: 10b6d801 align: 28
>> gran: 0 limit: ffffffcf done
>> avoid_fixed_resources: DOMAIN: 0000
>> avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
>> avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffcf
>> constrain_resources: DOMAIN: 0000
>> constrain_resources: PCI: 00:00.0
>> constrain_resources: PCI: 00:01.0
>> constrain_resources: PCI: 00:01.1
>> constrain_resources: PCI: 00:02.0
>> constrain_resources: PCI: 00:02.3
>> constrain_resources: PCI: 01:00.0
>> constrain_resources: PCI: 01:00.1
>> constrain_resources: PCI: 01:00.2
>> constrain_resources: PCI: 01:00.3
>> constrain_resources: PCI: 00:02.4
>> constrain_resources: PCI: 02:00.0
>> constrain_resources: PCI: 00:10.0
>> constrain_resources: PCI: 00:11.0
>> constrain_resources: PCI: 00:12.0
>> constrain_resources: PCI: 00:12.2
>> constrain_resources: PCI: 00:13.0
>> constrain_resources: PCI: 00:13.2
>> constrain_resources: PCI: 00:14.0
>> constrain_resources: I2C: 01:50
>> constrain_resources: I2C: 01:51
>> constrain_resources: PCI: 00:14.2
>> constrain_resources: PCI: 00:14.3
>> constrain_resources: PCI: 00:14.7
>> constrain_resources: PCI: 00:16.0
>> constrain_resources: PCI: 00:16.2
>> constrain_resources: PCI: 00:18.0
>> constrain_resources: PCI: 00:18.1
>> constrain_resources: PCI: 00:18.2
>> constrain_resources: PCI: 00:18.3
>> constrain_resources: PCI: 00:18.4
>> constrain_resources: PCI: 00:18.5
>> avoid_fixed_resources2: DOMAIN: 0000 at 10000000 limit 0000ffff
>> lim->base 00001000 lim->limit 0000ffff
>> avoid_fixed_resources2: DOMAIN: 0000 at 10000100 limit ffffffcf
>> lim->base 00000000 lim->limit ff7fffff
>> Setting resources...
>> DOMAIN: 0000 allocate_resources_io: base:1000 size:2428 align:12 gran:0
>> limit:ffff
>> Assigned: PCI: 00:02.3 1c * [0x1000 - 0x1fff] io
>> Assigned: PCI: 00:02.4 1c * [0x2000 - 0x2fff] io
>> Assigned: PCI: 00:01.0 20 * [0x3000 - 0x30ff] io
>> Assigned: PCI: 00:11.0 20 * [0x3400 - 0x340f] io
>> Assigned: PCI: 00:11.0 10 * [0x3410 - 0x3417] io
>> Assigned: PCI: 00:11.0 18 * [0x3418 - 0x341f] io
>> Assigned: PCI: 00:11.0 14 * [0x3420 - 0x3423] io
>> Assigned: PCI: 00:11.0 1c * [0x3424 - 0x3427] io
>> DOMAIN: 0000 allocate_resources_io: next_base: 3428 size: 2428 align: 12
>> gran: 0 done
>> PCI: 00:02.3 allocate_resources_io: base:1000 size:1000 align:12 gran:12
>> limit:ffff
>> Assigned: PCI: 01:00.0 10 * [0x1000 - 0x10ff] io
>> Assigned: PCI: 01:00.1 10 * [0x1400 - 0x14ff] io
>> Assigned: PCI: 01:00.2 10 * [0x1800 - 0x18ff] io
>> Assigned: PCI: 01:00.3 10 * [0x1c00 - 0x1cff] io
>> PCI: 00:02.3 allocate_resources_io: next_base: 1d00 size: 1000 align: 12
>> gran: 12 done
>> PCI: 00:02.4 allocate_resources_io: base:2000 size:1000 align:12 gran:12
>> limit:ffff
>> Assigned: PCI: 02:00.0 10 * [0x2000 - 0x20ff] io
>> PCI: 00:02.4 allocate_resources_io: next_base: 2100 size: 1000 align: 12
>> gran: 12 done
>> DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10b6d801 align:28
>> gran:0 limit:ff7fffff
>> Assigned: PCI: 00:01.0 10 * [0xe0000000 - 0xefffffff] prefmem
>> Assigned: PCI: 00:01.0 18 * [0xf0000000 - 0xf07fffff] prefmem
>> Assigned: PCI: 00:02.3 24 * [0xf0800000 - 0xf08fffff] prefmem
>> Assigned: PCI: 00:02.3 20 * [0xf0900000 - 0xf09fffff] mem
>> Assigned: PCI: 00:02.4 24 * [0xf0a00000 - 0xf0afffff] prefmem
>> Assigned: PCI: 00:01.0 24 * [0xf0b00000 - 0xf0b3ffff] mem
>> Assigned: PCI: 00:01.0 30 * [0xf0b40000 - 0xf0b5ffff] mem
>> Assigned: PCI: 00:01.1 10 * [0xf0b60000 - 0xf0b63fff] mem
>> Assigned: PCI: 00:14.2 10 * [0xf0b64000 - 0xf0b67fff] mem
>> Assigned: PCI: 00:10.0 10 * [0xf0b68000 - 0xf0b69fff] mem
>> Assigned: PCI: 00:12.0 10 * [0xf0b6a000 - 0xf0b6afff] mem
>> Assigned: PCI: 00:13.0 10 * [0xf0b6b000 - 0xf0b6bfff] mem
>> Assigned: PCI: 00:16.0 10 * [0xf0b6c000 - 0xf0b6cfff] mem
>> Assigned: PCI: 00:11.0 24 * [0xf0b6d000 - 0xf0b6d3ff] mem
>> Assigned: PCI: 00:12.2 10 * [0xf0b6d400 - 0xf0b6d4ff] mem
>> Assigned: PCI: 00:13.2 10 * [0xf0b6d500 - 0xf0b6d5ff] mem
>> Assigned: PCI: 00:14.7 10 * [0xf0b6d600 - 0xf0b6d6ff] mem
>> Assigned: PCI: 00:16.2 10 * [0xf0b6d700 - 0xf0b6d7ff] mem
>> Assigned: PCI: 00:14.3 a0 * [0xf0b6d800 - 0xf0b6d800] mem
>> DOMAIN: 0000 allocate_resources_mem: next_base: f0b6d801 size: 10b6d801
>> align: 28 gran: 0 done
>> PCI: 00:02.3 allocate_resources_prefmem: base:f0800000 size:100000 align:20
>> gran:20 limit:ff7fffff
>> Assigned: PCI: 01:00.0 20 * [0xf0800000 - 0xf0803fff] prefmem
>> PCI: 00:02.3 allocate_resources_prefmem: next_base: f0804000 size: 100000
>> align: 20 gran: 20 done
>> PCI: 00:02.3 allocate_resources_mem: base:f0900000 size:100000 align:20
>> gran:20 limit:ff7fffff
>> Assigned: PCI: 01:00.1 20 * [0xf0900000 - 0xf0903fff] mem
>> Assigned: PCI: 01:00.2 20 * [0xf0904000 - 0xf0907fff] mem
>> Assigned: PCI: 01:00.3 20 * [0xf0908000 - 0xf090bfff] mem
>> Assigned: PCI: 01:00.0 18 * [0xf090c000 - 0xf090cfff] mem
>> Assigned: PCI: 01:00.1 18 * [0xf090d000 - 0xf090dfff] mem
>> Assigned: PCI: 01:00.2 18 * [0xf090e000 - 0xf090efff] mem
>> Assigned: PCI: 01:00.3 18 * [0xf090f000 - 0xf090f0ff] mem
>> PCI: 00:02.3 allocate_resources_mem: next_base: f090f100 size: 100000 align:
>> 20 gran: 20 done
>> PCI: 00:02.4 allocate_resources_prefmem: base:f0a00000 size:100000 align:20
>> gran:20 limit:ff7fffff
>> Assigned: PCI: 02:00.0 20 * [0xf0a00000 - 0xf0a03fff] prefmem
>> Assigned: PCI: 02:00.0 18 * [0xf0a04000 - 0xf0a04fff] prefmem
>> PCI: 00:02.4 allocate_resources_prefmem: next_base: f0a05000 size: 100000
>> align: 20 gran: 20 done
>> PCI: 00:02.4 allocate_resources_mem: base:ff7fffff size:0 align:20 gran:20
>> limit:ff7fffff
>> PCI: 00:02.4 allocate_resources_mem: next_base: ff7fffff size: 0 align: 20
>> gran: 20 done
>> Root Device assign_resources, bus 0 link: 0
>> CPU_CLUSTER: 0 c0010058 <- [0x00a0000000 - 0x00afffffff] size 0x10000000
>> gran 0x00 mem <mmconfig>
>> CPU_CLUSTER: 0 assign_resources, bus 0 link: 0
>> CPU_CLUSTER: 0 assign_resources, bus 0 link: 0
>> node 0: mmio_basek=00380000, basek=00400000, limitk=00460000
>> CBMEM region bf13f000-bfffffff (cbmem_late_set_table)
>> DOMAIN: 0000 assign_resources, bus 0 link: 0
>> PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c
>> prefmem64
>> PCI: 00:01.0 18 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x17
>> prefmem64
>> PCI: 00:01.0 20 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08
>> io
>> PCI: 00:01.0 24 <- [0x00f0b00000 - 0x00f0b3ffff] size 0x00040000 gran 0x12
>> mem
>> PCI: 00:01.0 30 <- [0x00f0b40000 - 0x00f0b5ffff] size 0x00020000 gran 0x11
>> romem
>> PCI: 00:01.1 10 <- [0x00f0b60000 - 0x00f0b63fff] size 0x00004000 gran 0x0e
>> mem64
>> PCI: 00:02.3 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c
>> bus 01 io
>> PCI: 00:02.3 24 <- [0x00f0800000 - 0x00f08fffff] size 0x00100000 gran 0x14
>> bus 01 prefmem
>> PCI: 00:02.3 20 <- [0x00f0900000 - 0x00f09fffff] size 0x00100000 gran 0x14
>> bus 01 mem
>> PCI: 00:02.3 assign_resources, bus 1 link: 0
>> PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08
>> io
>> PCI: 01:00.0 18 <- [0x00f090c000 - 0x00f090cfff] size 0x00001000 gran 0x0c
>> mem64
>> PCI: 01:00.0 20 <- [0x00f0800000 - 0x00f0803fff] size 0x00004000 gran 0x0e
>> prefmem64
>> PCI: 01:00.1 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08
>> io
>> PCI: 01:00.1 18 <- [0x00f090d000 - 0x00f090dfff] size 0x00001000 gran 0x0c
>> mem64
>> PCI: 01:00.1 20 <- [0x00f0900000 - 0x00f0903fff] size 0x00004000 gran 0x0e
>> mem64
>> PCI: 01:00.2 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08
>> io
>> PCI: 01:00.2 18 <- [0x00f090e000 - 0x00f090efff] size 0x00001000 gran 0x0c
>> mem64
>> PCI: 01:00.2 20 <- [0x00f0904000 - 0x00f0907fff] size 0x00004000 gran 0x0e
>> mem64
>> PCI: 01:00.3 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08
>> io
>> PCI: 01:00.3 18 <- [0x00f090f000 - 0x00f090f0ff] size 0x00000100 gran 0x08
>> mem64
>> PCI: 01:00.3 20 <- [0x00f0908000 - 0x00f090bfff] size 0x00004000 gran 0x0e
>> mem64
>> PCI: 00:02.3 assign_resources, bus 1 link: 0
>> PCI: 00:02.4 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c
>> bus 02 io
>> PCI: 00:02.4 24 <- [0x00f0a00000 - 0x00f0afffff] size 0x00100000 gran 0x14
>> bus 02 prefmem
>> PCI: 00:02.4 20 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14
>> bus 02 mem
>> PCI: 00:02.4 assign_resources, bus 2 link: 0
>> PCI: 02:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08
>> io
>> PCI: 02:00.0 18 <- [0x00f0a04000 - 0x00f0a04fff] size 0x00001000 gran 0x0c
>> prefmem64
>> PCI: 02:00.0 20 <- [0x00f0a00000 - 0x00f0a03fff] size 0x00004000 gran 0x0e
>> prefmem64
>> PCI: 00:02.4 assign_resources, bus 2 link: 0
>> PCI: 00:10.0 10 <- [0x00f0b68000 - 0x00f0b69fff] size 0x00002000 gran 0x0d
>> mem64
>> PCI: 00:11.0 10 <- [0x0000003410 - 0x0000003417] size 0x00000008 gran 0x03
>> io
>> PCI: 00:11.0 14 <- [0x0000003420 - 0x0000003423] size 0x00000004 gran 0x02
>> io
>> PCI: 00:11.0 18 <- [0x0000003418 - 0x000000341f] size 0x00000008 gran 0x03
>> io
>> PCI: 00:11.0 1c <- [0x0000003424 - 0x0000003427] size 0x00000004 gran 0x02
>> io
>> PCI: 00:11.0 20 <- [0x0000003400 - 0x000000340f] size 0x00000010 gran 0x04
>> io
>> PCI: 00:11.0 24 <- [0x00f0b6d000 - 0x00f0b6d3ff] size 0x00000400 gran 0x0a
>> mem
>> PCI: 00:12.0 10 <- [0x00f0b6a000 - 0x00f0b6afff] size 0x00001000 gran 0x0c
>> mem
>> PCI: 00:12.2 EHCI Debug Port hook triggered
>> PCI: 00:12.2 10 <- [0x00f0b6d400 - 0x00f0b6d4ff] size 0x00000100 gran 0x08
>> mem
>> PCI: 00:12.2 EHCI Debug Port relocated
>> PCI: 00:13.0 10 <- [0x00f0b6b000 - 0x00f0b6bfff] size 0x00001000 gran 0x0c
>> mem
>> PCI: 00:13.2 10 <- [0x00f0b6d500 - 0x00f0b6d5ff] size 0x00000100 gran 0x08
>> mem
>> PCI: 00:14.2 10 <- [0x00f0b64000 - 0x00f0b67fff] size 0x00004000 gran 0x0e
>> mem64
>> PCI: 00:14.3 a0 <- [0x00f0b6d802 - 0x00f0b6d802] size 0x00000001 gran 0x00
>> mem
>> PCI: 00:14.7 10 <- [0x00f0b6d600 - 0x00f0b6d6ff] size 0x00000100 gran 0x08
>> mem64
>> PCI: 00:16.0 10 <- [0x00f0b6c000 - 0x00f0b6cfff] size 0x00001000 gran 0x0c
>> mem
>> PCI: 00:16.2 10 <- [0x00f0b6d700 - 0x00f0b6d7ff] size 0x00000100 gran 0x08
>> mem
>> DOMAIN: 0000 assign_resources, bus 0 link: 0
>> Root Device assign_resources, bus 0 link: 0
>> Done setting resources.
>> Show resources in subtree (Root Device)...After assigning values.
>> Root Device child on link 0 CPU_CLUSTER: 0
>> CPU_CLUSTER: 0 child on link 0 APIC: 00
>> CPU_CLUSTER: 0 resource base a0000000 size 10000000 align 0 gran 0 limit 0
>> flags f0000200 index c0010058
>> APIC: 00
>> APIC: 01
>> DOMAIN: 0000 child on link 0 PCI: 00:00.0
>> DOMAIN: 0000 resource base 1000 size 2428 align 12 gran 0 limit ffff flags
>> 40040100 index 10000000
>> DOMAIN: 0000 resource base e0000000 size 10b6d801 align 28 gran 0 limit
>> ff7fffff flags 40040200 index 10000100
>> DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags
>> e0004200 index 10
>> DOMAIN: 0000 resource base c0000 size dff40000 align 0 gran 0 limit 0
>> flags e0004200 index 20
>> DOMAIN: 0000 resource base 100000000 size 20000000 align 0 gran 0 limit 0
>> flags e0004200 index 30
>> DOMAIN: 0000 resource base c0000000 size 20000000 align 0 gran 0 limit 0
>> flags f0000200 index 7
>> PCI: 00:00.0
>> PCI: 00:01.0
>> PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit
>> ff7fffff flags 60001201 index 10
>> PCI: 00:01.0 resource base f0000000 size 800000 align 23 gran 23 limit
>> ff7fffff flags 60001201 index 18
>> PCI: 00:01.0 resource base 3000 size 100 align 8 gran 8 limit ffff flags
>> 60000100 index 20
>> PCI: 00:01.0 resource base f0b00000 size 40000 align 18 gran 18 limit
>> ff7fffff flags 60000200 index 24
>> PCI: 00:01.0 resource base f0b40000 size 20000 align 17 gran 17 limit
>> ff7fffff flags 60002200 index 30
>> PCI: 00:01.1
>> PCI: 00:01.1 resource base f0b60000 size 4000 align 14 gran 14 limit
>> ff7fffff flags 60000201 index 10
>> PCI: 00:02.0
>> PCI: 00:02.1
>> PCI: 00:02.2
>> PCI: 00:02.3 child on link 0 PCI: 01:00.0
>> PCI: 00:02.3 resource base 1000 size 1000 align 12 gran 12 limit ffff
>> flags 60080102 index 1c
>> PCI: 00:02.3 resource base f0800000 size 100000 align 20 gran 20 limit
>> ff7fffff flags 60081202 index 24
>> PCI: 00:02.3 resource base f0900000 size 100000 align 20 gran 20 limit
>> ff7fffff flags 60080202 index 20
>> PCI: 01:00.0
>> PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags
>> 60000100 index 10
>> PCI: 01:00.0 resource base f090c000 size 1000 align 12 gran 12 limit
>> ff7fffff flags 60000201 index 18
>> PCI: 01:00.0 resource base f0800000 size 4000 align 14 gran 14 limit
>> ff7fffff flags 60001201 index 20
>> PCI: 01:00.1
>> PCI: 01:00.1 resource base 1400 size 100 align 8 gran 8 limit ffff flags
>> 60000100 index 10
>> PCI: 01:00.1 resource base f090d000 size 1000 align 12 gran 12 limit
>> ff7fffff flags 60000201 index 18
>> PCI: 01:00.1 resource base f0900000 size 4000 align 14 gran 14 limit
>> ff7fffff flags 60000201 index 20
>> PCI: 01:00.2
>> PCI: 01:00.2 resource base 1800 size 100 align 8 gran 8 limit ffff flags
>> 60000100 index 10
>> PCI: 01:00.2 resource base f090e000 size 1000 align 12 gran 12 limit
>> ff7fffff flags 60000201 index 18
>> PCI: 01:00.2 resource base f0904000 size 4000 align 14 gran 14 limit
>> ff7fffff flags 60000201 index 20
>> PCI: 01:00.3
>> PCI: 01:00.3 resource base 1c00 size 100 align 8 gran 8 limit ffff flags
>> 60000100 index 10
>> PCI: 01:00.3 resource base f090f000 size 100 align 8 gran 8 limit
>> ff7fffff flags 60000201 index 18
>> PCI: 01:00.3 resource base f0908000 size 4000 align 14 gran 14 limit
>> ff7fffff flags 60000201 index 20
>> PCI: 00:02.4 child on link 0 PCI: 02:00.0
>> PCI: 00:02.4 resource base 2000 size 1000 align 12 gran 12 limit ffff
>> flags 60080102 index 1c
>> PCI: 00:02.4 resource base f0a00000 size 100000 align 20 gran 20 limit
>> ff7fffff flags 60081202 index 24
>> PCI: 00:02.4 resource base ff7fffff size 0 align 20 gran 20 limit
>> ff7fffff flags 60080202 index 20
>> PCI: 02:00.0
>> PCI: 02:00.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags
>> 60000100 index 10
>> PCI: 02:00.0 resource base f0a04000 size 1000 align 12 gran 12 limit
>> ff7fffff flags 60001201 index 18
>> PCI: 02:00.0 resource base f0a00000 size 4000 align 14 gran 14 limit
>> ff7fffff flags 60001201 index 20
>> PCI: 00:02.5
>> PCI: 00:10.0
>> PCI: 00:10.0 resource base f0b68000 size 2000 align 13 gran 13 limit
>> ff7fffff flags 60000201 index 10
>> PCI: 00:11.0
>> PCI: 00:11.0 resource base 3410 size 8 align 3 gran 3 limit ffff flags
>> 60000100 index 10
>> PCI: 00:11.0 resource base 3420 size 4 align 2 gran 2 limit ffff flags
>> 60000100 index 14
>> PCI: 00:11.0 resource base 3418 size 8 align 3 gran 3 limit ffff flags
>> 60000100 index 18
>> PCI: 00:11.0 resource base 3424 size 4 align 2 gran 2 limit ffff flags
>> 60000100 index 1c
>> PCI: 00:11.0 resource base 3400 size 10 align 4 gran 4 limit ffff flags
>> 60000100 index 20
>> PCI: 00:11.0 resource base f0b6d000 size 400 align 10 gran 10 limit
>> ff7fffff flags 60000200 index 24
>> PCI: 00:12.0
>> PCI: 00:12.0 resource base f0b6a000 size 1000 align 12 gran 12 limit
>> ff7fffff flags 60000200 index 10
>> PCI: 00:12.2
>> PCI: 00:12.2 resource base f0b6d400 size 100 align 8 gran 8 limit
>> ff7fffff flags 60000200 index 10
>> PCI: 00:13.0
>> PCI: 00:13.0 resource base f0b6b000 size 1000 align 12 gran 12 limit
>> ff7fffff flags 60000200 index 10
>> PCI: 00:13.2
>> PCI: 00:13.2 resource base f0b6d500 size 100 align 8 gran 8 limit
>> ff7fffff flags 60000200 index 10
>> PCI: 00:14.0 child on link 0 I2C: 01:50
>> I2C: 01:50
>> I2C: 01:51
>> PCI: 00:14.2
>> PCI: 00:14.2 resource base f0b64000 size 4000 align 14 gran 14 limit
>> ff7fffff flags 60000201 index 10
>> PCI: 00:14.3
>> PCI: 00:14.3 resource base f0b6d802 size 1 align 0 gran 0 limit ff7fffff
>> flags 60000200 index a0
>> PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
>> c0040100 index 10000000
>> PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
>> flags c0040200 index 10000100
>> PCI: 00:14.7
>> PCI: 00:14.7 resource base f0b6d600 size 100 align 8 gran 8 limit
>> ff7fffff flags 60000201 index 10
>> PCI: 00:16.0
>> PCI: 00:16.0 resource base f0b6c000 size 1000 align 12 gran 12 limit
>> ff7fffff flags 60000200 index 10
>> PCI: 00:16.2
>> PCI: 00:16.2 resource base f0b6d700 size 100 align 8 gran 8 limit
>> ff7fffff flags 60000200 index 10
>> PCI: 00:18.0
>> PCI: 00:18.1
>> PCI: 00:18.2
>> PCI: 00:18.3
>> PCI: 00:18.4
>> PCI: 00:18.5
>> Done allocating resources.
>> BS: BS_DEV_RESOURCES times (us): entry 0 run 1263543 exit 0
>> Enabling resources...
>>
>> Fam16 - domain_enable_resources: AmdInitMid.
>> agesawrapper_amdinitmid passed.
>> ader - leaving domain_enable_resources.
>> PCI: 00:00.0 cmd <- 04
>> PCI: 00:01.0 subsystem <- 1022/1410
>> PCI: 00:01.0 cmd <- 07
>> PCI: 00:01.1 subsystem <- 1022/1410
>> PCI: 00:01.1 cmd <- 02
>> PCI: 00:02.0 subsystem <- 1022/1410
>> PCI: 00:02.0 cmd <- 00
>> PCI: 00:02.3 bridge ctrl <- 0003
>> PCI: 00:02.3 cmd <- 07
>> PCI: 00:02.4 bridge ctrl <- 0003
>> PCI: 00:02.4 cmd <- 07
>> PCI: 00:10.0 subsystem <- 1022/1410
>> PCI: 00:10.0 cmd <- 02
>> PCI: 00:11.0 cmd <- 03
>> PCI: 00:12.0 subsystem <- 1022/1410
>> PCI: 00:12.0 cmd <- 02
>> PCI: 00:12.2 subsystem <- 1022/1410
>> PCI: 00:12.2 cmd <- 02
>> PCI: 00:13.0 subsystem <- 1022/1410
>> PCI: 00:13.0 cmd <- 02
>> PCI: 00:13.2 subsystem <- 1022/1410
>> PCI: 00:13.2 cmd <- 02
>> PCI: 00:14.0 subsystem <- 1022/1410
>> PCI: 00:14.0 cmd <- 403
>> PCI: 00:14.2 subsystem <- 1022/1410
>> PCI: 00:14.2 cmd <- 02
>> PCI: 00:14.3 subsystem <- 1022/1410
>> PCI: 00:14.3 cmd <- 0f
>> hudson_lpc_enable_childrens_resources
>> PCI: 00:14.7 cmd <- 06
>> PCI: 00:16.0 cmd <- 02
>> PCI: 00:16.2 cmd <- 02
>> PCI: 00:18.0 subsystem <- 1022/1410
>> PCI: 00:18.0 cmd <- 00
>> PCI: 00:18.1 subsystem <- 1022/1410
>> PCI: 00:18.1 cmd <- 00
>> PCI: 00:18.2 subsystem <- 1022/1410
>> PCI: 00:18.2 cmd <- 00
>> PCI: 00:18.3 subsystem <- 1022/1410
>> PCI: 00:18.3 cmd <- 00
>> PCI: 00:18.4 subsystem <- 1022/1410
>> PCI: 00:18.4 cmd <- 00
>> PCI: 00:18.5 subsystem <- 1022/1410
>> PCI: 00:18.5 cmd <- 00
>> PCI: 01:00.0 cmd <- 03
>> PCI: 01:00.1 cmd <- 03
>> PCI: 01:00.2 cmd <- 03
>> PCI: 01:00.3 cmd <- 03
>> PCI: 02:00.0 cmd <- 03
>> done.
>> BS: BS_DEV_ENABLE times (us): entry 0 run 84710 exit 0
>> Initializing devices...
>> Root Device init
>> Root Device init 910 usecs
>> CPU_CLUSTER: 0 init
>> start_eip=0x00001000, code_size=0x00000031
>> Initializing CPU #0
>> CPU: vendor AMD device 700f01
>> CPU: family 16, model 00, stepping 01
>> Using generic cpu ops (good)
>> Model 16 Init.
>>
>> MTRR check
>> Fixed MTRRs : Enabled
>> Variable MTRRs: Enabled
>>
> Does AGESA assign its own MTRRs? The only MTRR information I see is
> above that they are enabled. Not that this is your particular issue?
I do not know if AGESA assigns its own MTRRs. However, looking at the
log from a working Parmer system, this section is identical.
>> Enabling cache
>> Setting up local apic... apic_id: 0x00 done.
>> siblings = 01, CPU #0 initialized
>> CPU1: stack_base 002cb000, stack_end 002cbff8
>> Asserting INIT.
>> Waiting for send to finish...
>> +Deasserting INIT.
>> Waiting for send to finish...
>> +#startup loops: 2.
>> Sending STARTUP #1 to 1.
>> After apic_write.
>> Startup point 1.
>> Waiting for send to finish...
>> +Sending STARTUP #2 to 1.
>> After apic_write.
>> Startup point 1.
>> Waiting for send to finish...
>> +After Startup.
>> Initializing CPU #1
>> Waiting for 1 CPUS to stop
>> CPU: vendor AMD device 700f01
>> CPU: family 16, model 00, stepping 01
>> Using generic cpu ops (good)
>> Model 16 Init.
>>
>> MTRR check
>> Fixed MTRRs : Enabled
>> Variable MTRRs: Enabled
>>
>> Enabling cache
>> Setting up local apic... apic_id: 0x01 done.
>> siblings = 01, CPU #1 initialized
>> All AP CPUs stopped (1435 loops)
>> CPU1: stack: 002cb000 - 002cc000, lowest used address 002cbd9c, stack used:
>> 612 bytes
>> CPU_CLUSTER: 0 init 71485 usecs
>> PCI: 00:00.0 init
>> PCI: 00:00.0 init 935 usecs
>> PCI: 00:01.0 init
>> PCI: 00:01.0 init 935 usecs
>> PCI: 00:01.1 init
>> PCI: 00:01.1 init 935 usecs
>> PCI: 00:02.0 init
>> PCI: 00:02.0 init 935 usecs
>> PCI: 00:10.0 init
>> PCI: 00:10.0 init 935 usecs
>> PCI: 00:11.0 init
>> PCI: 00:11.0 init 939 usecs
>> PCI: 00:12.0 init
>> PCI: 00:12.0 init 935 usecs
>> PCI: 00:12.2 init
>> PCI: 00:12.2 init 935 usecs
>> PCI: 00:13.0 init
>> PCI: 00:13.0 init 935 usecs
>> PCI: 00:13.2 init
>> PCI: 00:13.2 init 935 usecs
>> PCI: 00:14.0 init
>> IOAPIC: Initializing IOAPIC at 0xfec00000
>> IOAPIC: Bootstrap Processor Local APIC = 0x00
>> IOAPIC: ID = 0x04
>> IOAPIC: Dumping registers
>> reg 0x0000: 0x04000000
>> reg 0x0001: 0x00178021
>> reg 0x0002: 0x04000000
>> IOAPIC: 24 interrupts
>> IOAPIC: Enabling interrupts on FSB
>> IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
>> IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
>> IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
>> IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
>> IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
>> IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
>> IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
>> IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
>> IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
>> PCI: 00:14.0 init 73107 usecs
>> PCI: 00:14.2 init
>> PCI: 00:14.2 init 998 usecs
>> PCI: 00:14.3 init
>> RTC Init
>> PCI: 00:14.3 init 1506 usecs
>> PCI: 00:14.7 init
>> PCI: 00:14.7 init 938 usecs
>> PCI: 00:16.0 init
>> PCI: 00:16.0 init 998 usecs
>> PCI: 00:16.2 init
>> PCI: 00:16.2 init 935 usecs
>> PCI: 00:18.0 init
>> PCI: 00:18.0 init 935 usecs
>> PCI: 00:18.1 init
>> PCI: 00:18.1 init 935 usecs
>> PCI: 00:18.2 init
>> PCI: 00:18.2 init 935 usecs
>> PCI: 00:18.3 init
>> PCI: 00:18.3 init 935 usecs
>> PCI: 00:18.4 init
>> PCI: 00:18.4 init 935 usecs
>> PCI: 00:18.5 init
>> PCI: 00:18.5 init 935 usecs
>> PCI: 01:00.0 init
>> PCI: 01:00.0 init 935 usecs
>> PCI: 01:00.1 init
>> PCI: 01:00.1 init 935 usecs
>> PCI: 01:00.2 init
>> PCI: 01:00.2 init 935 usecs
>> PCI: 01:00.3 init
>> PCI: 01:00.3 init 998 usecs
>> PCI: 02:00.0 init
>> PCI: 02:00.0 init 935 usecs
>> Devices initialized
>> Show all devs...After init.
>> Root Device: enabled 1
>> CPU_CLUSTER: 0: enabled 1
>> APIC: 00: enabled 1
>> DOMAIN: 0000: enabled 1
>> PCI: 00:00.0: enabled 1
>> PCI: 00:01.0: enabled 1
>> PCI: 00:01.1: enabled 1
>> PCI: 00:02.0: enabled 1
>> PCI: 00:02.1: enabled 0
>> PCI: 00:02.2: enabled 0
>> PCI: 00:02.3: enabled 1
>> PCI: 00:02.4: enabled 1
>> PCI: 00:02.5: enabled 0
>> PCI: 00:10.0: enabled 1
>> PCI: 00:11.0: enabled 1
>> PCI: 00:12.0: enabled 1
>> PCI: 00:12.2: enabled 1
>> PCI: 00:13.0: enabled 1
>> PCI: 00:13.2: enabled 1
>> PCI: 00:14.0: enabled 1
>> I2C: 01:50: enabled 1
>> I2C: 01:51: enabled 1
>> PCI: 00:14.2: enabled 1
>> PCI: 00:14.3: enabled 1
>> PCI: 00:14.7: enabled 1
>> PCI: 00:18.0: enabled 1
>> PCI: 00:18.1: enabled 1
>> PCI: 00:18.2: enabled 1
>> PCI: 00:18.3: enabled 1
>> PCI: 00:18.4: enabled 1
>> PCI: 00:18.5: enabled 1
>> APIC: 01: enabled 1
>> PCI: 00:16.0: enabled 1
>> PCI: 00:16.2: enabled 1
>> PCI: 01:00.0: enabled 1
>> PCI: 01:00.1: enabled 1
>> PCI: 01:00.2: enabled 1
>> PCI: 01:00.3: enabled 1
>> PCI: 02:00.0: enabled 1
>> BS: BS_DEV_INIT times (us): entry 0 run 262571 exit 0
>> CBMEM region bf13f000-bfffffff (cbmem_reinit)
>> CBMEM region bf13f000-bfffffff (cbmem_init)
>> Adding CBMEM entry as no. 1
>> Moving GDT to bf13f200...ok
>> Finalize devices...
>> Devices finalized
>> BS: BS_POST_DEVICE times (us): entry 7235 run 2058 exit 0
>> BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0
>> CBMEM Base is bf13f000.
>>
>> EventLog: EventClass = 2, EventInfo = 8040100.
>> Param1 = 1180000, Param2 = 0.
>> Param3 = 0, Param4 = 0.
>>
>> EventLog: EventClass = 2, EventInfo = 8040100.
>> Param1 = 1080000, Param2 = 0.
>> Param3 = 0, Param4 = 0.
>>
>> EventLog: EventClass = 2, EventInfo = 8040100.
>> Param1 = 1040000, Param2 = 0.
>> Param3 = 0, Param4 = 0.
>>
>> EventLog: EventClass = 2, EventInfo = 8040100.
>> Param1 = a008, Param2 = 0.
>> Param3 = 0, Param4 = 0.
>>
>> EventLog: EventClass = 2, EventInfo = 8040100.
>> Param1 = a00f, Param2 = 0.
>> Param3 = 0, Param4 = 0.
>>
>> EventLog: EventClass = 2, EventInfo = 8040100.
>> Param1 = a00e, Param2 = 0.
>> Param3 = 0, Param4 = 0.
>>
>> EventLog: EventClass = 2, EventInfo = 8040100.
>> Param1 = a010, Param2 = 0.
>> Param3 = 0, Param4 = 0.
>> ASSERTION FAILED: file 'src/mainboard/asrock/imb-a180/agesawrapper.c', line
>> 433
>> DmiTable:100123f8, AcpiPstatein: 10010129, AcpiSrat:0,AcpiSlit:0,
>> Mce:10010571, Cmc:10010633,Alib:10016141, AcpiIvrs:0 in
>> agesawrapper_amdinitlate
>> agesawrapper_amdinitlate failed: 5
>> NvStorageSize=3b4, NvStorage=1002111d
>> SF: Detected W25Q32 with page size 1000, total 400000
>> SF: Successfully erased 4096 bytes @ 0xffff7000
>> VolatileStorageSize=5556, VolatileStorage=100214d1
>> SF: Detected W25Q32 with page size 1000, total 400000
>> SF: Successfully erased 24576 bytes @ 0xffff0000
>> SF: Detected W25Q32 with page size 1000, total 400000
>> SF: Successfully erased 4096 bytes @ 0xffff6000
>> Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
>> Adding CBMEM entry as no. 2
>> Writing IRQ routing tables to 0xbf13f400...write_pirq_routing_table done.
>> PIRQ table: 48 bytes.
>> Wrote the mp table end at: 000f0410 - 000f061c
>> Adding CBMEM entry as no. 3
>> Wrote the mp table end at: bf140410 - bf14061c
>> MP table: 540 bytes.
>> Adding CBMEM entry as no. 4
>> ACPI: Writing ACPI tables at bf141400...
>> ACPI: * DSDT at bf1414c8
>> ACPI: * DSDT @ bf1414c8 Length 161b
>> ACPI: * FACS at bf142ae8
>> ACPI: * FADT at bf142b28
>> pm_base: 0x0800
>> ACPI: added table 1/32, length now 40
>> ACPI: * HPET at bf142c20
>> ACPI: added table 2/32, length now 44
>> ACPI: * MADT at bf142c58
>> ACPI: added table 3/32, length now 48
>> ACPI: added table 4/32, length now 52
>> ACPI: * IVRS at bf142e98
>> AGESA IVRS table NULL. Skipping.
>> ACPI: * SRAT at bf142e98
>> AGESA SRAT table NULL. Skipping.
>> ACPI: * SLIT at bf142e98
>> AGESA SLIT table NULL. Skipping.
>> ACPI: * AGESA ALIB SSDT at bf142ea0
>> ACPI: added table 5/32, length now 56
>> ACPI: * SSDT at bf147580
>> ACPI: added table 6/32, length now 60
>> ACPI: * SSDT for PState at bf1479bc
>> ACPI: * SSDT
>> ACPI: added table 7/32, length now 64
>> ACPI: done.
>> ACPI tables: 26113 bytes.
>> Adding CBMEM entry as no. 5
>> smbios_write_tables: bf14c800
>> Root Device (ASROCK IMB-A180)
>> CPU_CLUSTER: 0 (AMD FAM16 Root Complex)
>> APIC: 00 (AMD CPU Family 16h)
>> DOMAIN: 0000 (AMD FAM16 Root Complex)
>> PCI: 00:00.0 (AMD FAM16 Northbridge)
>> PCI: 00:01.0 (AMD FAM16 Northbridge)
>> PCI: 00:01.1 (AMD FAM16 Northbridge)
>> PCI: 00:02.0 (AMD FAM16 Northbridge)
>> PCI: 00:02.1 (AMD FAM16 Northbridge)
>> PCI: 00:02.2 (AMD FAM16 Northbridge)
>> PCI: 00:02.3 (AMD FAM16 Northbridge)
>> PCI: 00:02.4 (AMD FAM16 Northbridge)
>> PCI: 00:02.5 (AMD FAM16 Northbridge)
>> PCI: 00:10.0 (ATI HUDSON)
>> PCI: 00:11.0 (ATI HUDSON)
>> PCI: 00:12.0 (ATI HUDSON)
>> PCI: 00:12.2 (ATI HUDSON)
>> PCI: 00:13.0 (ATI HUDSON)
>> PCI: 00:13.2 (ATI HUDSON)
>> PCI: 00:14.0 (ATI HUDSON)
>> I2C: 01:50 (unknown)
>> I2C: 01:51 (unknown)
>> PCI: 00:14.2 (ATI HUDSON)
>> PCI: 00:14.3 (ATI HUDSON)
>> PCI: 00:14.7 (ATI HUDSON)
>> PCI: 00:18.0 (AMD FAM16 Northbridge)
>> PCI: 00:18.1 (AMD FAM16 Northbridge)
>> PCI: 00:18.2 (AMD FAM16 Northbridge)
>> PCI: 00:18.3 (AMD FAM16 Northbridge)
>> PCI: 00:18.4 (AMD FAM16 Northbridge)
>> PCI: 00:18.5 (AMD FAM16 Northbridge)
>> APIC: 01 (unknown)
>> PCI: 00:16.0 (unknown)
>> PCI: 00:16.2 (unknown)
>> PCI: 01:00.0 (unknown)
>> PCI: 01:00.1 (unknown)
>> PCI: 01:00.2 (unknown)
>> PCI: 01:00.3 (unknown)
>> PCI: 02:00.0 (unknown)
>> SMBIOS tables: 305 bytes.
>> Adding CBMEM entry as no. 6
>> Adding CBMEM entry as no. 7
>> Adding CBMEM entry as no. 8
>> Writing table forward entry at 0x00000500
>> Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5fdf
>> Table forward entry ends at 0x00000528.
>> ... aligned to 0x00001000
>> Writing coreboot table at 0xbffee000
>> rom_table_end = 0xbffee000
>> ... aligned to 0xbfff0000
>> 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
>> 1. 0000000000001000-000000000009ffff: RAM
>> 2. 00000000000c0000-000000009fffffff: RAM
>> 3. 00000000a0000000-00000000afffffff: RESERVED
>> 4. 00000000b0000000-00000000bf13efff: RAM
>> 5. 00000000bf13f000-00000000bfffffff: CONFIGURATION TABLES
>> 6. 00000000c0000000-00000000dfffffff: RESERVED
>> 7. 0000000100000000-000000011fffffff: RAM
>> Wrote coreboot table at: bffee000, 0x240 bytes, checksum d482
>> coreboot table: 600 bytes.
>> Multiboot Information structure has been written.
>> FREE SPACE 0. bfff6000 0000a000
>> GDT 1. bf13f200 00000200
>> IRQ TABLE 2. bf13f400 00001000
>> SMP TABLE 3. bf140400 00001000
>> ACPI 4. bf141400 0000b400
>> SMBIOS 5. bf14c800 00000800
>> ACPI RESUME 6. bf14d000 00e00000
>> ACPISCRATCH 7. bff4d000 000a1000
>> COREBOOT 8. bffee000 00008000
>> BS: BS_WRITE_TABLES times (us): entry 0 run 1009162 exit 0
>> Loading segment from rom address 0xffc0efb8
>> code (compression=1)
>> New segment dstaddr 0xe6b50 memsize 0x194b0 srcaddr 0xffc0eff0 filesize
>> 0xd2b6
>> (cleaned up) New segment addr 0xe6b50 size 0x194b0 offset 0xffc0eff0
>> filesize 0xd2b6
>> Loading segment from rom address 0xffc0efd4
>> Entry Point 0x000fc7a6
>> Loading Segment: addr: 0x00000000000e6b50 memsz: 0x00000000000194b0 filesz:
>> 0x000000000000d2b6
>> lb: [0x0000000000200000, 0x000000000038d034)
>> Post relocation: addr: 0x00000000000e6b50 memsz: 0x00000000000194b0 filesz:
>> 0x000000000000d2b6
>> using LZMA
>> [ 0x000e6b50, 00100000, 0x00100000) <- ffc0eff0
>> dest 000e6b50, end 00100000, bouncebuffer bee24f98
>> Loaded segments
>> BS: BS_PAYLOAD_LOAD times (us): entry 0 run 43665 exit 0
>> Jumping to boot code at 000fc7a6
>> CPU0: stack: 002cc000 - 002cd000, lowest used address 002cc670, stack used:
>> 2448 bytes
>> entry = 0x000fc7a6
>> lb_start = 0x00200000
>> lb_size = 0x0018d034
>> buffer = 0xbee24f98
>> AT+GCAP AT+GCAP AT+GCAP \00x\F0~\00x\F0~
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
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