[coreboot] Will coreboot work on Gigabyte GA-970A-UD3?

Wed Mar 27 11:10:24 CET 2013

Dear Chaser,

welcome to coreboot!

Am Mittwoch, den 27.03.2013, 07:39 +0200 schrieb Chaser:
> SUBJ. My computer:
> 1. Motherboard: Gigabyte GA-970A-UD3
> CPU: AMD Phenom II X4 965 (HDZ965FBGMBOX)
> GPU: Asus HD 7770 (HD7770-DC-1GD5-V2)
> Northbridge: AMD 970
> Southbridge: AMD SB950

I think these components are support, but not the board. You would need
to do the port for your board yourself. But as the chipset is already
supported, it is much less work than starting from nothing.

> 2. # lspci -tvnn
> -[0000:00]-+-00.0  Advanced Micro Devices [AMD] nee ATI RD890 PCI to
> PCI bridge (external gfx0 port B) [1002:5a14]
>            +-02.0-[01]--+-00.0  Advanced Micro Devices [AMD] nee ATI
> Cape Verde [Radeon HD 7700 Series] [1002:683d]

Please do not line wrap pasted sections.

[…]

> 3. Super I/O: iTE IT8720
> # superiotool -dV
> superiotool r

[…]

> Probing for ITE Super I/O (init=standard) at 0x2e...
> Found ITE IT8720F (id=0x8720, rev=0x8) at 0x2e
> Register dump:
> idx 20 21 22 23 24 2b
> val 87 20 08 00 00 00
> def 87 20 05 00 00 00
> LDN 0x00 (Floppy)
> idx 30 60 61 70 74 f0 f1
> val 00 00 00 00 04 00 80
> def 00 03 f0 06 02 00 00
> LDN 0x01 (COM1)
> idx 30 60 61 70 f0 f1
> val 01 03 f8 04 00 50
> def 00 03 f8 04 00 50
> LDN 0x02 (COM2)
> idx 30 60 61 70 f0 f1
> val 00 00 00 00 00 50
> def 00 02 f8 03 00 50
> LDN 0x03 (Parallel port)
> idx 30 60 61 62 63 70 74 f0
> val 00 00 00 00 00 00 04 08
> def 00 03 78 07 78 07 03 03
> LDN 0x04 (Environment controller)
> idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6
> val 01 02 28 00 00 00 80 00  0a 80 00 3e 1b
> def 00 02 90 02 30 09 00 00  00 00 00 NA NA
> LDN 0x05 (Keyboard)
> idx 30 60 61 62 63 70 71 f0
> val 01 00 60 00 64 01 02 48
> def 01 00 60 00 64 01 02 48
> LDN 0x06 (Mouse)
> idx 30 70 71 f0
> val 00 00 02 00
> def 00 0c 02 00
> LDN 0x07 (GPIO)
> idx 25 26 27 28 29 2a 2c 60  61 62 63 64 65 70 71 72  73 74 b0 b1 b2
> b3 b4 b5  b8 b9 ba bb bc bd c0 c1  c2 c3 c4 c8 c9 ca cb cc  e0 e1 e2
> e3 e4 e5 e6 e7  e9 f0 f1 f2 f3 f4 f5 f6  f7 f8 f9 fa fb fc fd fe  ff
> val 01 fb 06 40 00 00 03 00  00 02 20 00 00 00 01 00  38 00 00 00 00
> 00 00 00  80 69 00 40 01 00 01 82  06 00 00 00 03 06 00 00  00 00 00
> 00 00 00 00 00  00 00 00 00 00 00 00 26  00 00 01 00 00 ff 00 00  00
> def 00 ff 00 40 00 00 03 00  00 00 00 00 00 00 00 NA  38 00 00 00 00
> 00 00 00  20 00 00 00 00 00 01 00  00 40 00 01 00 00 40 00  00 00 00
> 00 00 00 00 00  NA 00 00 00 00 00 00 00  00 00 00 00 00 NA 00 00  00
> LDN 0x0a (Consumer IR)
> idx 30 60 61 70 f0
> val 00 03 10 0b 06
> def 00 03 10 0b 06

[…]

So this seems supported too, which is good.

> 4. # flashrom --programmer internal -V
> flashrom v0.9.6.1-r1564 on Linux 3.8.2-gentoo (x86_64)
> flashrom is free software, get the source code at http://www.flashrom.org
> 
> flashrom was built with libpci 3.1.10, GCC 4.7.2, little endian
> Command line (3 args): flashrom --programmer internal -V
> Calibrating delay loop... OS timer resolution is 1 usecs, 1443M loops
> per second, delay more than 10% too short (got 84% of expected delay),
> recalculating... 1331M loops per second, delay more than 10% too short
> (got 78% of expected delay), recalculating... 1559M loops per second,
> 10 myus = 9 us, 100 myus = 91 us, 1000 myus = 912 us, 10000 myus =
> 9119 us, 4 myus = 3 us, OK.
> Initializing internal programmer
> No coreboot table found.
> DMI string system-manufacturer: "Gigabyte Technology Co., Ltd."
> DMI string system-product-name: "GA-970A-UD3"
> DMI string system-version: " "
> DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd."
> DMI string baseboard-product-name: "GA-970A-UD3"
> DMI string baseboard-version: " "
> DMI string chassis-type: "Desktop"
> Found ITE Super I/O, ID 0x8720 on port 0x2e
> Found chipset "AMD SB7x0/SB8x0/SB9x0" with PCI ID 1002:439d. Enabling
> flash write... SPI base address is at 0xfec10000
> AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0
> PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1
> SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1,
> ArbWaitCount=7, SpiBridgeDisable=1, DropOneClkOnRd=0
> NormSpeed is 16.5 MHz
> GPIO11 used for SPI_DO
> GPIO12 used for SPI_DI
> GPIO31 used for SPI_HOLD
> GPIO32 used for SPI_CS
> GPIO47 used for SPI_CLK
> SB700 IMC is not active.
> ROM strap override is not active
> OK.
> No IT87* serial flash segment enabled.
> The following protocols are supported: LPC, FWH, SPI.

[…]

> Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
> Chip status register is 00
> Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000.

[…]

> Found Winbond flash chip "W25Q32" (4096 kB, SPI).
> This chip may contain one-time programmable memory. flashrom cannot read
> and may never be able to write it, hence it may not be able to completely
> clone the contents of this chip (see man page for details).
> No operations were specified.

So this looks also good.

> 5. Specs http://www.gigabyte.com/products/product-page.aspx?pid=3907#sp

To summarize, the board is not supported out of the box. You need to do
the work. Make sure you have a way to recover and a way to get debugging
messages (FAQ [1]). If you have specific questions, do not hesitate to
ask.

Thanks,

Paul

[1] http://www.coreboot.org/FAQ
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