[coreboot] New patch to review for coreboot: fde3707 Butterfly, Stout: Force SATA link speed to 3 Gbps

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Tue Mar 19 02:04:29 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2823

-gerrit

commit fde3707653bd57ea896df6e6da7497ab48339e33
Author: Shawn Nematbakhsh <shawnn at google.com>
Date:   Thu Mar 14 11:03:59 2013 -0700

    Butterfly, Stout: Force SATA link speed to 3 Gbps
    
    Force link speed on these platforms to 3 Gbps to defeat buggy SATA
    drives.
    
    Change-Id: Ia38a7c486fb1f4469cd67ca5244bbf61f877d556
    Signed-off-by: Shawn Nematbakhsh <shawnn at google.com>
---
 src/mainboard/google/butterfly/devicetree.cb | 5 ++++-
 src/mainboard/google/stout/devicetree.cb     | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index ca8118a..e7a50c0 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -58,7 +58,10 @@ chip northbridge/intel/sandybridge
 
 			register "ide_legacy_combined" = "0x0"
 			register "sata_ahci" = "0x1"
-			register "sata_port_map" = "0x3"	#enable SATA ports 0 & 1
+			# Enable SATA ports 0 & 1
+			register "sata_port_map" = "0x3"
+			# Set max SATA speed to 3.0 Gb/s
+			register "sata_interface_speed_support" = "0x2"
 
 			# Enable EC Port 0x68/0x6C
 			register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index c58a8d6..6e02020 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -60,6 +60,8 @@ chip northbridge/intel/sandybridge
 			register "ide_legacy_combined" = "0x0"
 			register "sata_ahci" = "0x1"
 			register "sata_port_map" = "0x3"
+			# Set max SATA speed to 3.0 Gb/s
+			register "sata_interface_speed_support" = "0x2"
 
 			# Enable EC Port 0x68/0x6C
 			register "gen1_dec" = "0x00040069"



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