[coreboot] New patch to review for coreboot: 9776a16 lynxpoint: Add function for checking for LP chipset

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2811

-gerrit

commit 9776a16d3c5edde2c25201bd384e25c61203065c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Mar 7 14:06:43 2013 -0800

    lynxpoint: Add function for checking for LP chipset
    
    Add a helper function pch_is_lp() that will return 1 if
    the current chipset is of the new "low power" variant used
    with Haswell ULT.
    
    Additionally these functions are added to SMM so it can
    be used there.
    
    Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/southbridge/intel/lynxpoint/Makefile.inc |  2 +-
 src/southbridge/intel/lynxpoint/pch.c        | 40 ++++++++++++++++++++--------
 src/southbridge/intel/lynxpoint/pch.h        | 13 +++++----
 3 files changed, 38 insertions(+), 17 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index fd5b4df..3710135 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -45,7 +45,7 @@ ramstage-y += spi.c
 smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
 
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c
 
 romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
 romstage-$(CONFIG_USBDEBUG) += usb_debug.c
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 41c596c..6f03716 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2012 The Chromium OS Authors.  All rights reserved.
+ * Copyright 2013 Google Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -21,36 +21,52 @@
 
 #include <console/console.h>
 #include <delay.h>
+#ifdef __SMM__
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#else /* !__SMM__ */
 #include <device/device.h>
 #include <device/pci.h>
+#endif
 #include "pch.h"
 
-static int pch_revision_id = -1;
-static int pch_type = -1;
+static device_t pch_get_lpc_device(void)
+{
+#ifdef __SMM__
+	return PCI_DEV(0, 0x1f, 0);
+#else
+	return dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+#endif
+}
 
 int pch_silicon_revision(void)
 {
+	static int pch_revision_id = -1;
+
 	if (pch_revision_id < 0)
-		pch_revision_id = pci_read_config8(
-			dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
-			PCI_REVISION_ID);
+		pch_revision_id = pci_read_config8(pch_get_lpc_device(),
+						   PCI_REVISION_ID);
 	return pch_revision_id;
 }
 
 int pch_silicon_type(void)
 {
+	static int pch_type = -1;
+
 	if (pch_type < 0)
-		pch_type = pci_read_config8(
-			dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
-			PCI_DEVICE_ID + 1);
+		pch_type = pci_read_config8(pch_get_lpc_device(),
+					    PCI_DEVICE_ID + 1);
 	return pch_type;
 }
 
-int pch_silicon_supported(int type, int rev)
+int pch_is_lp(void)
 {
-	return 1;
+	return pch_silicon_type() == PCH_TYPE_LPT_LP;
 }
 
+#ifndef __SMM__
+
 /* Set bit in Function Disble register to hide this device */
 static void pch_hide_devfn(unsigned devfn)
 {
@@ -444,3 +460,5 @@ struct chip_operations southbridge_intel_lynxpoint_ops = {
 	CHIP_NAME("Intel Series 8 (Lynx Point) Southbridge")
 	.enable_dev = pch_enable,
 };
+
+#endif /* __SMM__ */
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 563730e..38202b5 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -40,9 +40,9 @@
  * Bus 0:Device 28:Function 5 PCI Express Port 6
  * Bus 0:Device 28:Function 6 PCI Express Port 7
  * Bus 0:Device 28:Function 7 PCI Express Port 8
- * Bus 0:Device 27:Function 0 Intel® High Definition Audio Controller
+ * Bus 0:Device 27:Function 0 Intel High Definition Audio Controller
  * Bus 0:Device 25:Function 0 Gigabit Ethernet Controller
- * Bus 0:Device 22:Function 0 Intel® Management Engine Interface #1
+ * Bus 0:Device 22:Function 0 Intel Management Engine Interface #1
  * Bus 0:Device 22:Function 1 Intel Management Engine Interface #2
  * Bus 0:Device 22:Function 2 IDE-R
  * Bus 0:Device 22:Function 3 KT
@@ -50,6 +50,8 @@
 */
 
 /* PCH types */
+#define PCH_TYPE_LPT		0x8c
+#define PCH_TYPE_LPT_LP		0x9c
 
 /* PCH stepping values for LPC device */
 
@@ -125,13 +127,14 @@ struct rcba_config_instruction
 
 #if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
 void pch_config_rcba(const struct rcba_config_instruction *rcba_config);
+int pch_silicon_revision(void);
+int pch_silicon_type(void);
+int pch_is_lp(void);
+
 #if !defined(__PRE_RAM__) && !defined(__SMM__)
 #include <device/device.h>
 #include <arch/acpi.h>
 #include "chip.h"
-int pch_silicon_revision(void);
-int pch_silicon_type(void);
-int pch_silicon_supported(int type, int rev);
 void pch_enable(device_t dev);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 #if CONFIG_ELOG