[coreboot] New patch to review for coreboot: 4196a64 haswell: wait 10ms after INIT IPI
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Tue Mar 19 01:58:46 CET 2013
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2780
-gerrit
commit 4196a64aab245edcea4c93725ab817d9c527c2b7
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Jan 17 11:13:46 2013 -0600
haswell: wait 10ms after INIT IPI
There should be a fixed 10ms wait after sending an INIT IPI. The
previous implementation was just waiting up to 10ms for the IPI to
complete the send. That is not correct. The 10ms is unconditional
according to the documentation. No ill effects were observed with the
previous behavior, but it's important to follow the documentation.
Change-Id: Ib31d49ac74808f6eb512310e9f54a8f4abc3bfd7
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/cpu/intel/haswell/mp_init.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c
index b1567ba..3076d07 100644
--- a/src/cpu/intel/haswell/mp_init.c
+++ b/src/cpu/intel/haswell/mp_init.c
@@ -458,15 +458,8 @@ int start_aps(struct bus *cpu_bus, int ap_count)
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
LAPIC_DM_INIT);
- printk(BIOS_DEBUG, "Waiting for INIT to complete...");
-
- /* Wait for 10 ms to complete. */
- if (apic_wait_timeout(10000 /* 10 ms */, 100 /* us */)) {
- printk(BIOS_DEBUG, "timed out. Bailing. \n");
- return -1;
- } else {
- printk(BIOS_DEBUG, "done.\n");
- }
+ printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n");
+ mdelay(10);
/* Send 1st SIPI */
if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
More information about the coreboot
mailing list