[coreboot] New patch to review for coreboot: 75684e1 haswell: fix ACPI MCFG table

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Fri Mar 15 20:49:41 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2748

-gerrit

commit 75684e139163afce7bf268a49417dad749df2091
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jan 17 09:39:39 2013 -0600

    haswell: fix ACPI MCFG table
    
    The acpi_fill_mcfg() was still using ivy/sandy PCI device ids which Hawell
    obviously doesn't have. This resulted in an empty MCFG table. Instead of
    relying on PCI device ids use dev/fn 0/0 since that is where the host
    bridge always resides. Additionally remove the defines for the IB and SB
    pci device ids. Replace them with mobile and ult Haswel device ids and
    use those in the pci driver tables for the northbridge code.
    
    Booted to Linux and noted that MCFG was properly parsed.
    
    Change-Id: Ieaab2dfef0e9daf3edbd8a27efe0825d2beb9443
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/northbridge/intel/haswell/acpi.c        | 4 +---
 src/northbridge/intel/haswell/haswell.h     | 4 ++--
 src/northbridge/intel/haswell/northbridge.c | 4 ++--
 3 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index c616699..e4d86be 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -38,9 +38,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	u32 pciexbar_reg;
 	int max_buses;
 
-	dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SB, 0);
-	if (!dev)
-		dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IB, 0);
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!dev)
 		return current;
 
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index bbb51aa..3a18038 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -204,8 +204,8 @@ struct ied_header {
 	u8 reserved[34];
 } __attribute__ ((packed));
 
-#define PCI_DEVICE_ID_SB 0x0104
-#define PCI_DEVICE_ID_IB 0x0154
+#define PCI_DEVICE_ID_HSW_MOBILE 0x0c04
+#define PCI_DEVICE_ID_HSW_ULT 0x0a04
 
 #ifdef __SMM__
 void intel_northbridge_haswell_finalize_smm(void);
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index d20a40b..c8c1704 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -583,13 +583,13 @@ static struct device_operations mc_ops = {
 static const struct pci_driver mc_driver_hsw_mobile __pci_driver = {
 	.ops    = &mc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x0c04, /* Mobile Haswell */
+	.device = PCI_DEVICE_ID_HSW_MOBILE,
 };
 
 static const struct pci_driver mc_driver_hsw_ult __pci_driver = {
 	.ops    = &mc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x0a04, /* ULT Haswell */
+	.device = PCI_DEVICE_ID_HSW_ULT,
 };
 
 static void cpu_bus_init(device_t dev)



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