[coreboot] Could some one please give me parameters for QEMU for running Coreboot with Linux payload

Wed Mar 13 22:25:50 CET 2013

This is a qemu problem. Look at the end. It's trying to pxe boot. You
need to make it not do that.

ron

On Tue, Mar 12, 2013 at 8:32 AM, Pankaj Chhabra
<chhabra.pankaj at gmail.com> wrote:
> Hello,
>
> I have tested with coreboot and seabios with ROM size of 4M and it works
> fine.
>
> I am now running Qemu on Ubuntu 12.04 -
>
> Here is the coreboot+ Linux payload where the bios.bin points to
> coreboot.rom, I see the following on the terminal
>
> please check the log below and let me know if I am making any mistake -
>
>
> pankaj at ubuntu:/usr/share/qemu$ sudo qemu-system-i386 -serial stdio
>
> Could not access KVM kernel module: No such file or directory
> failed to initialize KVM: No such file or directory
> Back to tcg accelerator.
> POST: 0x05
>
>
> coreboot-4.0-3625-g5021209 Tue Mar 12 08:28:42 PDT 2013 starting...
> Re-Initializing CBMEM area to 0x17ee0000
> Initializing CBMEM area to 0x17ee0000 (1179648 bytes)
> Loading image.
> CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffc90/0x400000
> CBFS: CBFS location: 0x0~0x3ffcb0, align: 64
> CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0.
> CBFS:  - load entry 0x0 file name (16 bytes)...
> CBFS:  (unmatched file @0x0: cmos_layout.bin)
> CBFS:  - load entry 0x4c0 file name (32 bytes)...
> CBFS:  (unmatched file @0x4c0: fallback/romstage)
> CBFS:  - load entry 0x5000 file name (32 bytes)...
> CBFS: Found file (offset=0x5038, len=42816).
> CBFS: loading stage fallback/coreboot_ram @ 0x100000 (139264 bytes), entry @
> 0x100000
> CBFS: stage loaded.
> Jumping to image.
> POST: 0x80
> POST: 0x39
> coreboot-4.0-3625-g5021209 Tue Mar 12 08:28:42 PDT 2013 booting...
> POST: 0x40
> Enumerating buses...
> Show all devs...Before device enumeration.
> Root Device: enabled 1
> DOMAIN: 0000: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> Compare with tree...
> Root Device: enabled 1
>  DOMAIN: 0000: enabled 1
>   PCI: 00:00.0: enabled 1
>   PCI: 00:01.0: enabled 1
>   PCI: 00:01.1: enabled 1
> scan_static_bus for Root Device
> DOMAIN: 0000 enabled
> DOMAIN: 0000 scanning...
> PCI: pci_scan_bus for bus 00
> POST: 0x24
> PCI: 00:00.0 [8086/1237] ops
> PCI: 00:00.0 [8086/1237] enabled
> PCI: 00:01.0 [8086/7000] bus ops
> PCI: 00:01.0 [8086/7000] enabled
> PCI: 00:01.1 [8086/7010] ops
> PCI: 00:01.1 [8086/7010] enabled
> memalign Enter, boundary 8, size 152, free_mem_ptr 0011e000
> memalign 0011e000
> PCI: 00:01.3 [8086/7113] bus ops
> pwrmgt_enable: gpo default missing in devicetree.cb!
> Wakeup from ACPI sleep type S5 (PMCNTRL=0000)
> PCI: 00:01.3 [8086/7113] enabled
> memalign Enter, boundary 8, size 152, free_mem_ptr 0011e098
> memalign 0011e098
> PCI: 00:02.0 [1013/00b8] ops
> PCI: 00:02.0 [1013/00b8] enabled
> memalign Enter, boundary 8, size 152, free_mem_ptr 0011e130
> memalign 0011e130
> PCI: 00:03.0 [10ec/8139] enabled
> POST: 0x25
> scan_static_bus for PCI: 00:01.0
> scan_static_bus for PCI: 00:01.0 done
> scan_static_bus for PCI: 00:01.3
> scan_static_bus for PCI: 00:01.3 done
> PCI: pci_scan_bus returning with max=000
> POST: 0x55
> scan_static_bus for Root Device done
> done
> POST: 0x66
> found VGA at PCI: 00:02.0
> Setting up VGA for PCI: 00:02.0
> Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
> Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
> Allocating resources...
> Reading resources...
> Root Device read_resources bus 0 link: 0
> memalign Enter, boundary 8, size 2560, free_mem_ptr 0011e1c8
> memalign 0011e1c8
> DOMAIN: 0000 read_resources bus 0 link: 0
> DOMAIN: 0000 read_resources bus 0 link: 0 done
> Root Device read_resources bus 0 link: 0 done
> Done reading resources.
> Show resources in subtree (Root Device)...After reading.
>  Root Device child on link 0 DOMAIN: 0000
>   DOMAIN: 0000 child on link 0 PCI: 00:00.0
>   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags
> 40040100 index 10000000
>   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags
> 40040200 index 10000100
>   DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit
> ffffffff flags e0000200 index 2
>   DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit
> ffffffff flags e0000200 index 3
>    PCI: 00:00.0
>    PCI: 00:01.0
>    PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags
> c0000100 index 1
>    PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0
> flags d0000200 index 2
>    PCI: 00:01.1
>    PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100
> index 20
>    PCI: 00:01.3
>    PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags
> d0000100 index 1
>    PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags
> d0000100 index 2
>    PCI: 00:02.0
>    PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff
> flags 1200 index 10
>    PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
> flags 200 index 14
>    PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff
> flags 2200 index 30
>    PCI: 00:03.0
>    PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100
> index 10
>    PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
> 200 index 14
>    PCI: 00:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff
> flags 2200 index 30
> DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit:
> ffff
> PCI: 00:03.0 10 *  [0x0 - 0xff] io
> PCI: 00:01.1 20 *  [0x400 - 0x40f] io
> DOMAIN: 0000 compute_resources_io: base: 410 size: 410 align: 8 gran: 0
> limit: ffff done
> DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:
> ffffffff
> PCI: 00:02.0 10 *  [0x0 - 0x1ffffff] prefmem
> PCI: 00:02.0 30 *  [0x2000000 - 0x200ffff] mem
> PCI: 00:03.0 30 *  [0x2010000 - 0x201ffff] mem
> PCI: 00:02.0 14 *  [0x2020000 - 0x2020fff] mem
> PCI: 00:03.0 14 *  [0x2021000 - 0x20210ff] mem
> DOMAIN: 0000 compute_resources_mem: base: 2021100 size: 2021100 align: 25
> gran: 0 limit: ffffffff done
> avoid_fixed_resources: DOMAIN: 0000
> avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
> avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
> constrain_resources: DOMAIN: 0000
> constrain_resources: PCI: 00:00.0
> constrain_resources: PCI: 00:01.0
> constrain_resources: PCI: 00:01.1
> constrain_resources: PCI: 00:01.3
> constrain_resources: PCI: 00:02.0
> constrain_resources: PCI: 00:03.0
> avoid_fixed_resources2: DOMAIN: 0000 at 10000000 limit 0000ffff
> lim->base 00001000 lim->limit 0000e3ff
> avoid_fixed_resources2: DOMAIN: 0000 at 10000100 limit ffffffff
> lim->base 00000000 lim->limit febfffff
> Setting resources...
> DOMAIN: 0000 allocate_resources_io: base:1000 size:410 align:8 gran:0
> limit:e3ff
> Assigned: PCI: 00:03.0 10 *  [0x1000 - 0x10ff] io
> Assigned: PCI: 00:01.1 20 *  [0x1400 - 0x140f] io
> DOMAIN: 0000 allocate_resources_io: next_base: 1410 size: 410 align: 8 gran:
> 0 done
> DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2021100 align:25
> gran:0 limit:febfffff
> Assigned: PCI: 00:02.0 10 *  [0xfc000000 - 0xfdffffff] prefmem
> Assigned: PCI: 00:02.0 30 *  [0xfe000000 - 0xfe00ffff] mem
> Assigned: PCI: 00:03.0 30 *  [0xfe010000 - 0xfe01ffff] mem
> Assigned: PCI: 00:02.0 14 *  [0xfe020000 - 0xfe020fff] mem
> Assigned: PCI: 00:03.0 14 *  [0xfe021000 - 0xfe0210ff] mem
> DOMAIN: 0000 allocate_resources_mem: next_base: fe021100 size: 2021100
> align: 25 gran: 0 done
> Root Device assign_resources, bus 0 link: 0
> Detected 393216 Kbytes (384 MiB) RAM.
> DOMAIN: 0000 assign_resources, bus 0 link: 0
> PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04
> io
> PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19
> prefmem
> PCI: 00:02.0 14 <- [0x00fe020000 - 0x00fe020fff] size 0x00001000 gran 0x0c
> mem
> PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10
> romem
> PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08
> io
> PCI: 00:03.0 14 <- [0x00fe021000 - 0x00fe0210ff] size 0x00000100 gran 0x08
> mem
> PCI: 00:03.0 30 <- [0x00fe010000 - 0x00fe01ffff] size 0x00010000 gran 0x10
> romem
> DOMAIN: 0000 assign_resources, bus 0 link: 0
> Root Device assign_resources, bus 0 link: 0
> Done setting resources.
> Show resources in subtree (Root Device)...After assigning values.
>  Root Device child on link 0 DOMAIN: 0000
>   DOMAIN: 0000 child on link 0 PCI: 00:00.0
>   DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit e3ff flags
> 40040100 index 10000000
>   DOMAIN: 0000 resource base fc000000 size 2021100 align 25 gran 0 limit
> febfffff flags 40040200 index 10000100
>   DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit
> ffffffff flags e0000200 index 2
>   DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit
> ffffffff flags e0000200 index 3
>   DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags
> e0004200 index a
>   DOMAIN: 0000 resource base c0000 size 17f40000 align 0 gran 0 limit 0
> flags e0004200 index b
>    PCI: 00:00.0
>    PCI: 00:01.0
>    PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags
> c0000100 index 1
>    PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0
> flags d0000200 index 2
>    PCI: 00:01.1
>    PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit e3ff flags
> 60000100 index 20
>    PCI: 00:01.3
>    PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags
> d0000100 index 1
>    PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags
> d0000100 index 2
>    PCI: 00:02.0
>    PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit
> febfffff flags 60001200 index 10
>    PCI: 00:02.0 resource base fe020000 size 1000 align 12 gran 12 limit
> febfffff flags 60000200 index 14
>    PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit
> febfffff flags 60002200 index 30
>    PCI: 00:03.0
>    PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags
> 60000100 index 10
>    PCI: 00:03.0 resource base fe021000 size 100 align 8 gran 8 limit
> febfffff flags 60000200 index 14
>    PCI: 00:03.0 resource base fe010000 size 10000 align 16 gran 16 limit
> febfffff flags 60002200 index 30
> Done allocating resources.
> POST: 0x88
> Enabling resources...
> PCI: 00:00.0 cmd <- 00
> PCI: 00:01.0 cmd <- 00
> PCI: 00:01.1 cmd <- 01
> PCI: 00:01.3 cmd <- 00
> PCI: 00:02.0 cmd <- 03
> PCI: 00:03.0 cmd <- 03
> done.
> POST: 0x89
> Initializing devices...
> Root Device init
> PCI: 00:00.0 init
> Keyboard init...
> Setting up ethernet...
> Assigning IRQ 11 to 0:3.0
> i8259_configure_irq_trigger: current interrupts are 0x0
> i8259_configure_irq_trigger: try to set interrupts 0x800
> PCI: 00:01.0 init
> RTC Init
> PCI: 00:01.1 init
> IDE: Primary IDE interface: on
> IDE: Secondary IDE interface: on
> IDE: Access to legacy IDE ports: off
> PCI: 00:02.0 init
> CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffc90/0x400000
> CBFS: CBFS location: 0x0~0x3ffcb0, align: 64
> CBFS: Looking for 'pci1013,00b8.rom' starting from 0x0.
> CBFS:  - load entry 0x0 file name (16 bytes)...
> CBFS:  (unmatched file @0x0: cmos_layout.bin)
> CBFS:  - load entry 0x4c0 file name (32 bytes)...
> CBFS:  (unmatched file @0x4c0: fallback/romstage)
> CBFS:  - load entry 0x5000 file name (32 bytes)...
> CBFS:  (unmatched file @0x5000: fallback/coreboot_ram)
> CBFS:  - load entry 0xf780 file name (32 bytes)...
> CBFS:  (unmatched file @0xf780: fallback/payload)
> CBFS:  - load entry 0x147980 file name (16 bytes)...
> CBFS:  (unmatched file @0x147980: config)
> CBFS:  - load entry 0x148500 file name (16 bytes)...
> CBFS:  (unmatched file @0x148500: )
> CBFS: ERROR: No file header found at 0x3ffc80 - try next aligned address:
> 0x3ffcc0.
> CBFS: ERROR: Not found.
> CBFS: Could not find file 'pci1013,00b8.rom'.
> Option ROM address for PCI: 00:02.0 = fe000000
> PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x010f
> PCI ROM image, vendor ID 1013, device ID 00b8,
> PCI ROM image, Class Code 030000, Code Type 00
> Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes
> Real mode stub @00000600: 867 bytes
> Calling Option ROM...
> ... Option ROM returned.
> PCI: 00:03.0 init
> CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffc90/0x400000
> CBFS: CBFS location: 0x0~0x3ffcb0, align: 64
> CBFS: Looking for 'pci10ec,8139.rom' starting from 0x0.
> CBFS:  - load entry 0x0 file name (16 bytes)...
> CBFS:  (unmatched file @0x0: cmos_layout.bin)
> CBFS:  - load entry 0x4c0 file name (32 bytes)...
> CBFS:  (unmatched file @0x4c0: fallback/romstage)
> CBFS:  - load entry 0x5000 file name (32 bytes)...
> CBFS:  (unmatched file @0x5000: fallback/coreboot_ram)
> CBFS:  - load entry 0xf780 file name (32 bytes)...
> CBFS:  (unmatched file @0xf780: fallback/payload)
> CBFS:  - load entry 0x147980 file name (16 bytes)...
> CBFS:  (unmatched file @0x147980: config)
> CBFS:  - load entry 0x148500 file name (16 bytes)...
> CBFS:  (unmatched file @0x148500: )
> CBFS: ERROR: No file header found at 0x3ffc80 - try next aligned address:
> 0x3ffcc0.
> CBFS: ERROR: Not found.
> CBFS: Could not find file 'pci10ec,8139.rom'.
> Option ROM address for PCI: 00:03.0 = fe010000
> PCI expansion ROM, signature 0xaa55, INIT size 0xfc00, data ptr 0x0020
> PCI ROM image, vendor ID 10ec, device ID 8139,
> PCI ROM image, Class Code 000002, Code Type 00
> Class Code mismatch ROM 00000002, dev 00020000
> Copying non-VGA ROM image from fe010000 to 000d0000, 0xfc00 bytes
> Real mode stub @00000600: 867 bytes
> Calling Option ROM...
>
>
> iPXE (http://ipxe.org) 00:03.0 D000 D000
> Press Ctrl-B to configure iPXE (PCI 00:03.0)...
>
>
>
> Thanks,
> Pankaj
>
> On Tue, Mar 12, 2013 at 7:53 PM, ron minnich <rminnich at gmail.com> wrote:
>>
>> have you tested with coreboot&seabios and a rom size of 4M?
>>
>> ron
>
>