[coreboot] New patch to review for coreboot: a2f354d Revert "Intel Sandybridge: add reserved memory as resources"
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Wed Mar 13 20:25:14 CET 2013
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2709
-gerrit
commit a2f354d7ffbee4d55f7fe237786538a3fa0d478d
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Wed Mar 13 20:25:13 2013 +0100
Revert "Intel Sandybridge: add reserved memory as resources"
This reverts commit 1ec5e744c63938aa75e80e8d7548d05e998660a2
This is not to be submitted, but there as a place holder for the real fix.
Change-Id: I6a36b1b78423b5a79fa42b39927fbefef554aa48
---
src/cpu/x86/mtrr/mtrr.c | 4 ----
src/include/device/device.h | 12 ++---------
src/include/device/resource.h | 1 -
src/northbridge/intel/sandybridge/northbridge.c | 28 +++++++++++++------------
4 files changed, 17 insertions(+), 28 deletions(-)
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index a061b54..fdc7aa6 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -361,10 +361,6 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
return;
}
- if (res->flags & IORESOURCE_IGNORE_MTRR) {
- return;
- }
-
if (!(res->flags & IORESOURCE_CACHEABLE))
return;
diff --git a/src/include/device/device.h b/src/include/device/device.h
index eaf84c6..1515b45 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -173,25 +173,17 @@ unsigned int scan_static_bus(device_t bus, unsigned int max);
void fixed_mem_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek, unsigned long type);
-
-/* It is the caller's responsibility to adjust regions such that ram_resource()
- * and mmio_resource() do not overlap.
- *
- * Current MTRR setup creates exclusive uncacheable holes for uma_resource()
- * only and these are allowed to overlap any ram_resource(). This approach
- * is used for all UMA except Intel Sandy/IvyBridge.
- */
#define ram_resource(dev, idx, basek, sizek) \
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
#define bad_ram_resource(dev, idx, basek, sizek) \
- fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR)
+ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_CACHEABLE )
#define uma_resource(dev, idx, basek, sizek) \
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB)
#define mmio_resource(dev, idx, basek, sizek) \
- fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR)
+ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE)
void tolm_test(void *gp, struct device *dev, struct resource *new);
u32 find_pci_tolm(struct bus *bus);
diff --git a/src/include/device/resource.h b/src/include/device/resource.h
index c28ada5..e667f91 100644
--- a/src/include/device/resource.h
+++ b/src/include/device/resource.h
@@ -21,7 +21,6 @@
*/
#define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */
#define IORESOURCE_UMA_FB 0x00100000 /* UMA framebuffer */
-#define IORESOURCE_IGNORE_MTRR 0x00200000 /* The resource does not affect MTRR setup. */
#define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */
#define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 0df85a7..bfb2166 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -63,6 +63,19 @@ static const int legacy_hole_size_k = 384;
int add_northbridge_resources(struct lb_memory *mem)
{
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ legacy_hole_base_k * 1024, legacy_hole_size_k * 1024);
+
+#if CONFIG_CHROMEOS_RAMOOPS
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ CONFIG_CHROMEOS_RAMOOPS_RAM_START,
+ CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE);
+#endif
+
+ /* Required for SandyBridge sighting 3715511 */
+ lb_add_memory_range(mem, LB_MEM_RESERVED, 0x20000000, 0x00200000);
+ lb_add_memory_range(mem, LB_MEM_RESERVED, 0x40000000, 0x00200000);
+
return 0;
}
@@ -113,7 +126,7 @@ static void add_fixed_resources(struct device *dev, int index)
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
"size=0x%llx\n", uma_memory_base, uma_memory_size);
- resource = new_resource(dev, index++);
+ resource = new_resource(dev, index);
resource->base = (resource_t) uma_memory_base;
resource->size = (resource_t) uma_memory_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
@@ -126,23 +139,12 @@ static void add_fixed_resources(struct device *dev, int index)
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size);
- resource = new_resource(dev, index++);
+ resource = new_resource(dev, index+1);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-
- mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
-
-#if CONFIG_CHROMEOS_RAMOOPS
- mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
- CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
-#endif
-
- /* Required for SandyBridge sighting 3715511 */
- bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
- bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
}
static void pci_domain_set_resources(device_t dev)
More information about the coreboot
mailing list