[coreboot] New patch to review for coreboot: 8de4930 i82801gx bd82x6x: Enable PCI-to-PCI bridge
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Mar 13 11:49:04 CET 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2706
-gerrit
commit 8de4930c8071310205e6c0f2238639499c27e321
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Mar 13 11:12:56 2013 +0200
i82801gx bd82x6x: Enable PCI-to-PCI bridge
Once the PCI command register is written bridge forwards future IO
and memory regions, as programmed in the respective base and limit
registers, to the secondary PCI bus.
Since LPC function claims the resources for IOAPIC, ROM and
low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI
configuration will not overlap those regions and does not hide
the resources mentioned in the original comment.
Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/southbridge/intel/bd82x6x/pci.c | 9 ---------
src/southbridge/intel/i82801gx/pci.c | 9 ---------
2 files changed, 18 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index 306e7d5..0f5f3f6 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -63,7 +63,6 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, SECSTS, reg16);
}
-#undef PCI_BRIDGE_UPDATE_COMMAND
static void ich_pci_dev_enable_resources(struct device *dev)
{
const struct pci_operations *ops;
@@ -83,16 +82,8 @@ static void ich_pci_dev_enable_resources(struct device *dev)
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
-#ifdef PCI_BRIDGE_UPDATE_COMMAND
- /* If we write to PCI_COMMAND, on some systems
- * this will cause the ROM and APICs not being visible
- * anymore.
- */
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
-#else
- printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
-#endif
}
static void ich_pci_bus_enable_resources(struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index 0f372e7..5a21b21 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -62,7 +62,6 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, SECSTS, reg16);
}
-#undef PCI_BRIDGE_UPDATE_COMMAND
static void ich_pci_dev_enable_resources(struct device *dev)
{
const struct pci_operations *ops;
@@ -80,16 +79,8 @@ static void ich_pci_dev_enable_resources(struct device *dev)
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
-#ifdef PCI_BRIDGE_UPDATE_COMMAND
- /* If we write to PCI_COMMAND, on some systems
- * this will cause the ROM and APICs not being visible
- * anymore.
- */
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
-#else
- printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
-#endif
}
static void ich_pci_bus_enable_resources(struct device *dev)
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