[coreboot] New patch to review for coreboot: fc29761 amdk8: Increase limits for MMIO to TOLM..MMCONF

yhlu yinghailu at gmail.com
Wed Mar 13 04:31:14 CET 2013

On Tue, Mar 12, 2013 at 4:16 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Hash: SHA1
> Am 12.03.2013 22:28, schrieb yhlu:
>> On Tue, Mar 12, 2013 at 7:04 AM, Patrick Georgi
>> <gerrit at coreboot.org> wrote:
>>> as in our case, a bug in the coreboot resource allocator that
>>> leaves devices unallocated.
>> What is the bar address?
> 0 - thinking about it, there's the other possibility that the (custom)
> hardware in question takes longer to enable its PCIe side which didn't
> matter on the PCBIOS system it was developed on since that took long
> enough to boot.

I mean register index in pci config space.

is it in 0x10 to 0x30? or 0x184 or 0x190 etc?



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