[coreboot] Patch set updated for coreboot: a2456e1 OT200: reset MFGTP7 (backlight pwm)

Christian Gmeiner (christian.gmeiner@gmail.com) gerrit at coreboot.org
Tue Mar 12 10:46:13 CET 2013

Christian Gmeiner (christian.gmeiner at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2527


commit a2456e189efc5f861a8459b6913f34e0dbf1411f
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date:   Tue Mar 12 11:07:07 2013 +0100

    OT200: reset MFGTP7 (backlight pwm)
    The CS5536 companion device has three different power domains.
    * working domain
    * standby domain
    * RTC domain
    When the system is "off" only the standby domain is powered.
    MFGPT[7:6] are member of the standby power domain.
    MFGPT7 is used to control the backlight of the device and so the
    timer gets used and configured during system boot. If the system
    does a reboot the timer stays configured and the Linux driver
    can not use it:
       "ot200-backlight: ot200-backlight.0: MFGPT 7 not availale"
    The cs5535-mfgpt has a function to hard-reset all MFGPTs but the
    system hangs after the first access to a MFGPT register - cause
     * This is a sledgehammer that resets all MFGPT timers. This is required by
     * some broken BIOSes which leave the system in an unstable state
     * (TinyBIOS 0.98, for example; fixed in 0.99).  It's uncertain as to
     * whether or not this secret MSR can be used to release individual timers.
     * Jordan tells me that he and Mitch once played w/ it, but it's unclear
     * what the results of that were (and they experienced some instability).
    static void reset_all_timers(void)
    	uint32_t val, dummy;
    	/* The following undocumented bit resets the MFGPT timers */
    	val = 0xFF; dummy = 0;
    	wrmsr(MSR_MFGPT_SETUP, val, dummy);
    After playing around with this undocumented MSR it looks like I only
    need to set bit 7 to free the MFGPT7.
    BTW, all MFGPT[0:5] will be reset during pll_reset().
    Change-Id: I54a8d479ce495b0fc2f54db766a8d793bbb5d704
    Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
 src/mainboard/bachmann/ot200/mainboard.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c
index ac6855a..0ea053a 100644
--- a/src/mainboard/bachmann/ot200/mainboard.c
+++ b/src/mainboard/bachmann/ot200/mainboard.c
@@ -21,6 +21,7 @@
 #include <device/smbus.h>
 #include <smbios.h>
 #include <console/console.h>
+#include <cpu/x86/msr.h>
 /* overwrite a weak function to fill SMBIOS table with a custom value */
 static u8 hw_rev = 0;
@@ -43,6 +44,7 @@ static void init(struct device *dev)
 	unsigned int i;
 	u32 chksum = 0;
 	char block[20];
+	msr_t reset;
 	device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52);
 	if (eeprom_dev == 0) {
@@ -63,6 +65,12 @@ static void init(struct device *dev)
 	hw_rev = block[5];
 	printk(BIOS_DEBUG, "hw revision: %u\n", hw_rev);
+	/* Reset MFGPT7 (standby power domain) - this is done via
+	 * an undocumented register */
+	reset = rdmsr(0x5140002b);
+	reset.lo |= 1 << 7;
+	wrmsr(0x5140002b, reset);
 static void mainboard_enable(struct device *dev)

More information about the coreboot mailing list