[coreboot] New patch to review for coreboot: c6739e8 lynxpoint: PMIR register rename

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2619

-gerrit

commit c6739e8eb9a4961ac54223c8946d53e24d349142
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Nov 2 09:10:30 2012 -0500

    lynxpoint: PMIR register rename
    
    The register that controls global reset is named the Power
    Mangement Initialization Regiser (PMIR). Update the defines
    to reflect the documentation.
    
    Additionally, there is no core well reset control according to the
    EDS. There is, however, a CF9 lock field to lock this register down.
    
    Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/southbridge/intel/lynxpoint/early_me.c | 11 ++++-------
 src/southbridge/intel/lynxpoint/pch.h      |  6 +++---
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index 5b266cc..3e3c08d 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -111,18 +111,15 @@ int intel_early_me_uma_size(void)
 
 static inline void set_global_reset(int enable)
 {
-	u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
-
-	/* Clear CF9 Without Resume Well Reset Enable */
-	etr3 &= ~ETR3_CWORWRE;
+	u32 pmir = pci_read_config32(PCH_LPC_DEV, PMIR);
 
 	/* CF9GR indicates a Global Reset */
 	if (enable)
-		etr3 |= ETR3_CF9GR;
+		pmir |= PMIR_CF9GR;
 	else
-		etr3 &= ~ETR3_CF9GR;
+		pmir &= ~PMIR_CF9GR;
 
-	pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+	pci_write_config32(PCH_LPC_DEV, PMIR, pmir);
 }
 
 int intel_early_me_init_done(u8 status)
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index d508214..0847956 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -129,9 +129,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
 #define GEN_PMCON_1		0xa0
 #define GEN_PMCON_2		0xa2
 #define GEN_PMCON_3		0xa4
-#define ETR3			0xac
-#define  ETR3_CWORWRE		(1 << 18)
-#define  ETR3_CF9GR		(1 << 20)
+#define PMIR			0xac
+#define  PMIR_CF9LOCK		(1 << 31)
+#define  PMIR_CF9GR		(1 << 20)
 
 /* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD	(1 << 2)