[coreboot] Patch merged into coreboot/master: 4733c64 Persimmon DSDT: Add secondary bus range to PCI0

gerrit at coreboot.org gerrit at coreboot.org
Fri Mar 8 23:59:14 CET 2013

the following patch was just integrated into master:
commit 4733c647bc64cef86f03efd64a145e4da6fef123
Author: Mike Loptien <mike.loptien at se-eng.com>
Date:   Tue Mar 5 14:21:28 2013 -0700

    Persimmon DSDT: Add secondary bus range to PCI0
    Adding the 'WordBusNumber' macro to the PCI0
    CRES ResourceTemplate in the Persimmon DSDT.
    This sets up the bus number for the PCI0 device
    and the secondary bus number in the CRS method.
    This change came in response to a 'dmesg' error
    which states:
    '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
    By adding the 'WordBusNumber' macro, ACPI can set
    up a valid range for the PCIe downstream busses,
    thereby relieving the Linux kernel from "guessing"
    the valid range based off _BBN or assuming [0-0xFF].
    The Linux kernel code that checks this bus range is
    in `drivers/acpi/pci_root.c`.  PCI busses can have
    up to 256 secondary busses connected to them via
    a PCI-PCI bridge.  However, these busses do not
    have to be sequentially numbered, so leaving out a
    section of the range (eg. allowing [0-0x7F]) will
    unnecessarily restrict the downstream busses.
    This change will apply to other AMD mainboards and
    will be in a different commit.
    Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860
    Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
    Reviewed-on: http://review.coreboot.org/2592
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth at se-eng.com>
    Reviewed-by: Marc Jones <marc.jones at se-eng.com>

Build-Tested: build bot (Jenkins) at Fri Mar  8 01:00:19 2013, giving +1
Reviewed-By: Marc Jones <marc.jones at se-eng.com> at Fri Mar  8 23:59:13 2013, giving +2
See http://review.coreboot.org/2592 for details.


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