[coreboot] Patch merged into coreboot/master: 3914a31 AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio

gerrit at coreboot.org gerrit at coreboot.org
Wed Mar 6 19:07:30 CET 2013

the following patch was just integrated into master:
commit 3914a316c3d3ab1ba45fe33394f37aaefdc62d61
Author: Jens Rottmann <JRottmann at LiPPERTembedded.de>
Date:   Tue Feb 19 15:01:06 2013 +0100

    AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio
    The power up default for the 14M_25M_48M_OSC switchable clock output ball of
    the SB800 chipset is 14 MHz.  sb800/bootblock.c changes this to 48 MHz,
    which is the correct value for almost all SIOs.  However, not for
    'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not
    configurable for other clock speeds.  A wrong SIO clock supply results in
    funny RS232 output (wrong bit speed) and non-working PS/2.
    We could switch back to 14 MHz in the mainboard's romstage.c, but then the
    clock frequency would change twice.  The resulting short 48 MHz burst causes
    a handful of rubbish characters on RS232 on every boot until the SIO clock
    has stabilized again.
    This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz.
    This does not affect any boards currently in the repository (yet).
    Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4
    Signed-off-by: Jens Rottmann <JRottmann at LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2454
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth at se-eng.com>

Build-Tested: build bot (Jenkins) at Tue Feb 26 11:42:37 2013, giving +1
See http://review.coreboot.org/2454 for details.


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