[coreboot] New patch to review for coreboot: b319776 Supermicro H8QGI: set up right frequency limits for memory controller
Aladyshev Konstantin (kostr@list.ru)
gerrit at coreboot.org
Wed Mar 6 18:44:29 CET 2013
Aladyshev Konstantin (kostr at list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2589
-gerrit
commit b319776457fc96a861e7e7fb92424c178cd7cef9
Author: Konstantin Aladyshev <aladyshev at nicevt.ru>
Date: Wed Mar 6 21:39:40 2013 +0400
Supermicro H8QGI: set up right frequency limits for memory controller
According to BKDG:
"Memory controller (MCT) and DRAM controllers (DCTs) additions:
• Support for 933 MHz (1866 MT/s) MEMCLK frequency."
Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57
Signed-off-by: Konstantin Aladyshev <aladyshev at nicevt.ru>
---
src/mainboard/supermicro/h8qgi/buildOpts.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index 37ead99..7584e4f 100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -94,7 +94,7 @@
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
@@ -110,7 +110,7 @@
#define BLDCFG_ONLINE_SPARE FALSE
#define BLDCFG_BANK_SWIZZLE TRUE
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
#define BLDCFG_USE_BURST_MODE FALSE
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