[coreboot] Patch set updated for coreboot: 7f9f5f8 google/snow: Change MMC0 to work in 8 bit mode.

[Hung-Te Lin (hungte@chromium.org)]

Hung-Te Lin (hungte at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2585

-gerrit

commit 7f9f5f80c9dc5de2ebfdfa9927d19f1454b47785
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Mon Mar 4 16:39:35 2013 -0800

    google/snow: Change MMC0 to work in 8 bit mode.
    
    The MMC0 on google/snow can run in 8 bit mode. To simplify driver development,
    we explicitly disabled it (using zero, which runs in 1-bit / 4-bit mode) before.
    The 8 bit mode is ready now.
    
    Verified to boot on google/snow, and got MMC0 working.
    
    Change-Id: Ic0acc723fe6a8aecf373429d3801beadd70815d9
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
 src/mainboard/google/snow/romstage.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 7e1cd57..25c0846 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -53,7 +53,7 @@ static int board_wakeup_permitted(void)
 #endif
 
 static void initialize_s5p_mshc(void) {
-	/* MMC0: Fixed, support 8 bit mode, connected with GPIO. */
+	/* MMC0: Fixed, 8 bit mode, connected with GPIO. */
 	if (clock_set_mshci(PERIPH_ID_SDMMC0))
 		printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n");
 	if (gpio_direction_output(MMC0_GPIO_PIN, 1)) {
@@ -61,9 +61,7 @@ static void initialize_s5p_mshc(void) {
 	}
 	gpio_set_pull(MMC0_GPIO_PIN, EXYNOS_GPIO_PULL_NONE);
 	gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X);
-	/* TODO(hungte) Change 0 to PINMUX_FLAG_8BIT_MODE when the s5p_mshc
-	 * driver is ready. */
-	exynos_pinmux_config(PERIPH_ID_SDMMC0, 0);
+	exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 
 	/* MMC2: Removable, 4 bit mode, no GPIO. */
 	clock_set_mshci(PERIPH_ID_SDMMC2);