[coreboot] New patch to review for coreboot: 7ffb646 FrontRunner/Toucan-AF: work around AGESA RAM init crashing on reboot

[Jens Rottmann (JRottmann@LiPPERTembedded.de)]

Jens Rottmann (JRottmann at LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2573

-gerrit

commit 7ffb64659207545a8d59fac812f4e4883755d2bf
Author: Jens Rottmann <JRottmann at LiPPERTembedded.de>
Date:   Fri Mar 1 19:01:00 2013 +0100

    FrontRunner/Toucan-AF: work around AGESA RAM init crashing on reboot
    
    If you try to reset the system with outb(3,0x92), outb(4,0xcf9) or a
    triple-fault it will instead crash with a messy screen.  As the more common
    outb(0xFE, 0x64) doesn't work with our setup, Linux will crash whenever you
    ask it to reboot.  Closer inspection shows that on a warm boot of Coreboot
    agesawrapper_amdinitpost() always fails with error code 7.  Looks like DDR3
    re-init goes wrong somehow.  I tried find the reason for this but was
    unable to.  I am convinced this is not board specific but a bug in AGESA.
    
    In the end I had to settle for a workaround:  if amdinitpost returns 7 this
    patch resets the system harder with outb(0x06, 0x0cf9), after that RAM init
    will succeed.  As amdinitpost is early in POST this automatic reset is
    quick enough not to be noticable.
    
    I'd perfer a real fix, but that's all I have.
    
    Change-Id: I4763254b489f42a135232e45328ecf0d5c4d961a
    Signed-off-by: Jens Rottmann <JRottmann at LiPPERTembedded.de>
---
 src/mainboard/lippert/frontrunner-af/romstage.c | 4 ++++
 src/mainboard/lippert/toucan-af/romstage.c      | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index e5b3aeb..14a003a 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -113,6 +113,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		post_code(0x40);
 		printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 		val = agesawrapper_amdinitpost ();
+		/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
+		 * hang, looks like DRAM re-init goes wrong, don't know why. */
+		if (val == 7) /* fatal, amdinitenv below is going to hang */
+			outb(0x06, 0x0cf9); /* reset system harder instead */
 		if (val)
 			printk(BIOS_DEBUG, "error level: %x \n", val);
 		else
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 7d11813..fcec303 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -113,6 +113,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		post_code(0x40);
 		printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 		val = agesawrapper_amdinitpost ();
+		/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
+		 * hang, looks like DRAM re-init goes wrong, don't know why. */
+		if (val == 7) /* fatal, amdinitenv below is going to hang */
+			outb(0x06, 0x0cf9); /* reset system harder instead */
 		if (val)
 			printk(BIOS_DEBUG, "error level: %x \n", val);
 		else