[coreboot] Patch merged into coreboot/master: f12e561 armv7/snow: Add S5P MSHC initialization in ROM stage.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f12e56181788387c560c9b8d0f3d61fce4a4333a
Author: Hung-Te Lin <hungte at chromium.org>
Date:   Fri Mar 1 10:34:04 2013 +0800

    armv7/snow: Add S5P MSHC initialization in ROM stage.
    
    The SD/MMC interface on Exynos 5250 must be first configured with, GPIO, and
    pinmux settings before it can be detected and used in ramstage / payload.
    
    Verified on armv7/snow and successfully boot into ramstage.
    
    Change-Id: I26669eaaa212ab51ca72e8b7712970639a24e5c5
    Signed-off-by: Hung-Te Lin <hungte at chromium.org>
    Reviewed-on: http://review.coreboot.org/2561
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Fri Mar  1 03:56:51 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Fri Mar  1 06:53:57 2013, giving +2
See http://review.coreboot.org/2561 for details.

-gerrit