[coreboot] Samsung 550 Chromebook own Coreboot

[Aaron Durbin]

On Wed, Jul 31, 2013 at 10:18 AM, Aaron Durbin <adurbin at chromium.org> wrote:
> On Wed, Jul 31, 2013 at 10:00 AM, John Lewis <jlewis at johnlewis.ie> wrote:
>> On 31/07/2013 15:33, Aaron Durbin wrote:
>>
>>> On Wed, Jul 31, 2013 at 9:24 AM, John Lewis <jlewis at johnlewis.ie> wrote:
>>>
>>>> Hi all, Just want to confirm where we are in terms of things working or
>>>> not. The new system-agent binary works and recognises all 4 GB of RAM
>>>> as long as an additional pei data field is added to Stefan's patches in
>>>> http://review.coreboot.org/#/c/3831/ [1] as detailed by Kyösti in the
>>>> comments. The patches in http://review.coreboot.org/#/c/3830/ [2] don't
>>>>
>>>> appear to do anything for mrc.cache (it's still zero size) and this (or
>>>> perhaps something else) results in a time to SeaBIOS prompt of between
>>>> 5 to 9 seconds.
>>>
>>>
>>> Can you show us 'ls -l $(obj)/mrc.cache' ? I didn't see
>>
>>
>> -rw-rw-r--. 1 john john 0 Jul 31 11:04 mrc.cache
>
> This is your problem. I was hoping for a build.log that was completely
> clean. The build log attached does not show mrc.cache being created.
>
> Can you try the following and rebuilt?
> dd if=/dev/zero of=mrc.cache bs=16K count=1 | tr '\000' '\377' > mrc.cache

Apologies. I am doing too many things at once. Remove the
'of=mrc.cache' parameter to dd.
>
>>
>>
>>> CONFIG_MRC_CACHE_SIZE in your .config. Also, what does 'cbfstool
>>
>>
>> Menuconfig doesn't allow you specify it, and there isn't currently a default
>> being put in automatically.
>>
>>
>>> image.rom print' say now? Build logs with V=1 would be helpful to see
>>
>>
>> coreboot.rom: 8192 kB, bootblocksize 1552, romsize 8388608, offset 0x700000
>> alignment: 64 bytes
>>
>>
>> Name                           Offset     Type         Size
>> cmos_layout.bin                0x700000   cmos_layout  1120
>> pci8086,0106.rom               0x7004c0   optionrom    65536
>> cpu_microcode_blob.bin         0x710500   microcode    20544
>> fallback/romstage              0x7155c0   stage        36438
>> fallback/coreboot_ram          0x71e480   stage        294016
>> fallback/payload               0x766140   payload      87816
>> (empty)                        0x77b880   null         18200
>>
>> mrc.cache                      0x77ffc0   (unknown)    0
>> (empty)                        0x780000   null         130968
>> mrc.bin                        0x79ffc0   (unknown)    195732
>> (empty)                        0x7cfcc0   null         49880
>> spd.bin                        0x7dbfc0   (unknown)    1536
>> (empty)                        0x7dc600   null         144280
>>
>>
>>> what is occurring when mrc.cache is being created.
>>
>>
>> See attached build.log
>>
>>>
>>>> I added a 64 GB SSD this afternoon, which I have working, but something
>>>> strange went on with geometry - if I tried to dd the partition itself
>>>> back it would crap out at 2 GB (this was after dd'ing the backed up mbr
>>>> onto the new drive). If I dd'ed the whole device it worked, but the
>>>> partition wouldn't mount, and fdisk would report that the partition was
>>>> too large for the device. Luckily, after reboot, it worked anyway. :)
>>>> Summary: if we could get rid of the 5 to 9 second delay, and just
>>>> confirm the drive detection geometry is A1 I think we are there. John.
>>>> -- coreboot mailing list: coreboot at coreboot.org [3]
>>>> http://www.coreboot.org/mailman/listinfo/coreboot [4]