[coreboot] New patch to review for coreboot: 00dcf5a WIP: armv7/snow patch dump
David Hendricks (dhendrix@chromium.org)
gerrit at coreboot.org
Fri Jan 18 05:56:48 CET 2013
David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2174
-gerrit
commit 00dcf5a703e522b3b69485d5cc4af481c3be5fb0
Author: David Hendricks <dhendrix at chromium.org>
Date: Thu Jan 17 20:52:21 2013 -0800
WIP: armv7/snow patch dump
** do not submit **
This is just a patch dump so others can more easily get up to speed.
Magic offsets still need to be fixed, but at least we're finding our
ROM stage location and jumping to it. Unfortunately we never actually
seem to make it into romstage...
The user should see a bunch of prints to the UART, and PSHOLD will
be held high so the machine should not turn itself off.
Depends-On: 2173
Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d
Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
src/arch/armv7/bootblock_simple.c | 4 +-
src/arch/armv7/include/arch/cbfs.h | 46 +++++++++++++++++----
src/arch/armv7/include/arch/hlt.h | 1 -
src/arch/armv7/romstage.ld | 4 +-
src/cpu/samsung/exynos5250/bootblock.c | 3 +-
src/mainboard/google/snow/bootblock.c | 18 +++++----
src/mainboard/google/snow/romstage.c | 74 ++++++++++++++++++++++++++++++++++
7 files changed, 129 insertions(+), 21 deletions(-)
diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c
index 6897e15..de6269a 100644
--- a/src/arch/armv7/bootblock_simple.c
+++ b/src/arch/armv7/bootblock_simple.c
@@ -39,12 +39,12 @@ void main(unsigned long bist)
unsigned long entry;
if (boot_cpu()) {
- bootblock_mainboard_init();
bootblock_cpu_init();
+ bootblock_mainboard_init();
}
entry = findstage(target1);
+ printk(BIOS_INFO, "entry: 0x%08lx\n", entry);
if (entry) call(entry);
-
hlt();
}
diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h
index 0affa5e..f19e7e6 100644
--- a/src/arch/armv7/include/arch/cbfs.h
+++ b/src/arch/armv7/include/arch/cbfs.h
@@ -28,40 +28,72 @@
static int cbfs_check_magic(struct cbfs_file *file)
{
- return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0;
+ return strcmp(file->magic, CBFS_FILE_MAGIC) ? 0 : 1;
}
static unsigned long findstage(const char* target)
{
unsigned long offset, align;
/* FIXME: magic offsets */
- struct cbfs_header *header = (struct cbfs_header *)(0x02023400 + 0x40);
+ struct cbfs_header *header = (struct cbfs_header *)(0x02062040);
// if (ntohl(header->magic) != CBFS_HEADER_MAGIC)
// printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n");
offset = ntohl(header->offset);
align = ntohl(header->align);
+ printk(BIOS_INFO, "cbfs header (%p)\n", header);
+ printk(BIOS_INFO, "\tmagic: 0x%08x\n", ntohl(header->magic));
+ printk(BIOS_INFO, "\tversion: 0x%08x\n", ntohl(header->version));
+ printk(BIOS_INFO, "\tromsize: 0x%08x\n", ntohl(header->romsize));
+ printk(BIOS_INFO, "\tbootblocksize: 0x%08x\n", ntohl(header->bootblocksize));
+ printk(BIOS_INFO, "\talign: 0x%08x\n", ntohl(header->align));
+ printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(header->offset));
while(1) {
struct cbfs_file *file;
- file = (struct cbfs_file *)(offset + CONFIG_ROMSTAGE_BASE);
- if (!cbfs_check_magic(file))
+ file = (struct cbfs_file *)(offset + 0x02060000);
+ if (!cbfs_check_magic(file)) {
+ printk(BIOS_INFO, "magic is wrong, file: %p\n", file);
return 0;
- if (!strcmp(CBFS_NAME(file), target))
+ }
+ if (!strcmp(CBFS_NAME(file), target)) {
+ printk(BIOS_INFO, "CBFS name matched, offset: %p\n", file);
+ printk(BIOS_INFO, "\tmagic: %02x%02x%02x%02x%02x%02x%02x%02x\n",
+ file->magic[0], file->magic[1], file->magic[2], file->magic[3],
+ file->magic[4], file->magic[5], file->magic[6], file->magic[7]);
+ printk(BIOS_INFO, "\tlen: 0x%08x\n", ntohl(file->len));
+ printk(BIOS_INFO, "\ttype: 0x%08x\n", ntohl(file->type));
+ printk(BIOS_INFO, "\tchecksum: 0x%08x\n", ntohl(file->checksum));
+ printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(file->offset));
return (unsigned long)CBFS_SUBHEADER(file);
+ }
int flen = ntohl(file->len);
int foffset = ntohl(file->offset);
unsigned long oldoffset = offset;
offset = ALIGN(offset + foffset + flen, align);
+ printk(BIOS_INFO, "offset: 0x%08lx\n", offset);
if (offset <= oldoffset)
return 0;
- if (offset < CONFIG_ROMSTAGE_BASE + ntohl(header->romsize));
+ if (offset > (128 * 1024))
return 0;
}
}
static inline void call(unsigned long addr)
{
- void (*doit)(void) = (void *)addr;
+ __attribute__((noreturn)) void (*doit)(void) = (void *)addr;
+ printk(BIOS_INFO, "addr: %08lx, doit: %p\n", addr, doit);
+#if 0
+ /* FIXME: dumping SRAM content for sanity checking */
+// int i;
+ for (i = 0; i < 0x10000; i++) {
+ if (i % 16 == 0)
+ printk(BIOS_INFO, "\n0x%08lx: ", addr + i);
+ else
+ printk(BIOS_INFO, " ");
+ printk(BIOS_INFO, "%02x", *(uint8_t *)(addr + i));
+ }
+#endif
+ /* FIXME: do we need to change to/from arm/thumb? */
doit();
}
#endif
diff --git a/src/arch/armv7/include/arch/hlt.h b/src/arch/armv7/include/arch/hlt.h
index 535508a..285b6f8 100644
--- a/src/arch/armv7/include/arch/hlt.h
+++ b/src/arch/armv7/include/arch/hlt.h
@@ -4,7 +4,6 @@
static inline __attribute__((always_inline)) void hlt(void)
{
for (;;) ;
- //asm("hlt");
}
#endif /* ARCH_HLT_H */
diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld
index d40d2ef..bf1b094 100644
--- a/src/arch/armv7/romstage.ld
+++ b/src/arch/armv7/romstage.ld
@@ -35,11 +35,11 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
-/* ENTRY(_start) */
+ENTRY(_start)
SECTIONS
{
- . = 0x02023400 + 0x4000;
+ . = 0x02065438;
.romtext . : {
_rom = .;
diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c
index 0d65676..2852764 100644
--- a/src/cpu/samsung/exynos5250/bootblock.c
+++ b/src/cpu/samsung/exynos5250/bootblock.c
@@ -36,5 +36,6 @@ static int config_branch_prediction(int set_cr_z)
void bootblock_cpu_init(void);
void bootblock_cpu_init(void)
{
- /* FIXME: this is a stub for now */
+ volatile unsigned long *pshold = (unsigned long *)0x1004330c;
+ *pshold |= 0x100;
}
diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c
index a025b28..48854a7 100644
--- a/src/mainboard/google/snow/bootblock.c
+++ b/src/mainboard/google/snow/bootblock.c
@@ -42,8 +42,6 @@
#define EXYNOS5_CLOCK_BASE 0x10010000
-volatile unsigned long *pshold = (unsigned long *)0x1004330c;
-
/* FIXME(dhendrix): Can we move this SPI stuff elsewhere? */
static void spi_rx_tx(struct exynos_spi *regs, int todo,
void *dinp, void const *doutp, int i)
@@ -723,6 +721,9 @@ static void exynos5_uart_tx_byte(unsigned char data)
// struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
struct s5p_uart *uart = (struct s5p_uart *)uart3_base;
+ if (data == '\n')
+ exynos5_uart_tx_byte('\r');
+
/* wait for room in the tx FIFO */
while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) {
if (exynos5_uart_err_check(1))
@@ -738,12 +739,13 @@ void puts(const char *s)
int n = 0;
while (*s) {
+ if (*s == '\n') {
+ exynos5_uart_tx_byte(0xd); /* CR */
+ }
+
exynos5_uart_tx_byte(*s++);
n++;
}
-
- exynos5_uart_tx_byte(0xd); /* CR */
- exynos5_uart_tx_byte(0xa); /* LF */
}
static void do_serial(void)
@@ -2140,7 +2142,7 @@ void bootblock_mainboard_init(void)
printk(BIOS_INFO, "%s: hello world\n", __func__);
/* Copy romstage data from SPI ROM to SRAM */
- /* FIXME: test with something benign, then fix the offsets once
- we're more confident in this */
- copy_romstage(0x2000, 0x2060000, 0x800);
+ /* FIXME: magic offsets */
+ copy_romstage(0x0, 0x2060000, 0x10000);
+ printk(BIOS_INFO, "%s: goodbye world\n", __func__);
}
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 9092b7c..3cc71e0 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -21,12 +21,86 @@
#include <system.h>
#include <cache.h>
+#include <arch/io.h>
+
+/* FIXME: make i2c.h use standard types */
+#define uchar unsigned char
+#define uint unsigned int
+#include <device/i2c.h>
+
+#include <cpu/samsung/s5p-common/s3c24x0_i2c.h>
+#include "cpu/samsung/exynos5250/dmc.h"
+#include <cpu/samsung/exynos5250/power.h>
+#include <cpu/samsung/exynos5250/clock_init.h>
+#include <cpu/samsung/exynos5-common/uart.h>
+#include <console/console.h>
+
static void mmu_setup(void)
{
dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
}
+#define RX_FIFO_COUNT_MASK 0xff
+#define RX_FIFO_FULL_MASK (1 << 8)
+#define TX_FIFO_FULL_MASK (1 << 24)
+static uint32_t uart3_base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+
+static int exynos5_uart_err_check(int op)
+{
+ //struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
+ struct s5p_uart *uart = (struct s5p_uart *)uart3_base;
+ unsigned int mask;
+
+ /*
+ * UERSTAT
+ * Break Detect [3]
+ * Frame Err [2] : receive operation
+ * Parity Err [1] : receive operation
+ * Overrun Err [0] : receive operation
+ */
+ if (op)
+ mask = 0x8;
+ else
+ mask = 0xf;
+
+ return readl(&uart->uerstat) & mask;
+}
+
+/*
+ * Output a single byte to the serial port.
+ */
+static void exynos5_uart_tx_byte(unsigned char data)
+{
+// struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
+ struct s5p_uart *uart = (struct s5p_uart *)uart3_base;
+
+ if (data == '\n')
+ exynos5_uart_tx_byte('\r');
+
+ /* wait for room in the tx FIFO */
+ while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) {
+ if (exynos5_uart_err_check(1))
+ return;
+ }
+
+ writeb(data, &uart->utxh);
+}
+
void main(void)
{
+ int i;
+ char hello[] = "hello from romstage";
+// volatile unsigned long *pshold = (unsigned long *)0x1004330c;
+// i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+// power_init();
+// clock_init();
+// exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+// console_init();
+ printk(BIOS_INFO, "hello from romstage\n");
+ for (i = 0; i < 19; i++)
+ exynos5_uart_tx_byte(hello[i]);
+ exynos5_uart_tx_byte('\r');
+
+// *pshold &= ~0x100; /* shut down */
mmu_setup();
}
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