[coreboot] Patch set updated for coreboot: 8262e76 Hudson: Changes to agesa/hudson FADT for ACPI 3.0

Martin Roth (martin.roth@se-eng.com) gerrit at coreboot.org
Wed Jan 16 17:57:49 CET 2013


Martin Roth (martin.roth at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2140

-gerrit

commit 8262e7667fb0b5af392be59adfc4d67a339d9e92
Author: Martin Roth <martin at se-eng.com>
Date:   Thu Jan 10 16:40:59 2013 -0700

    Hudson: Changes to agesa/hudson FADT for ACPI 3.0
    
    Update the southbridge/amd/agesa/hudson FADT generation for ACPI
    3.0 compiance similar to what was done for cimx/SB800/fadt.c in
    commit 9aa43892e68
    
    According to the datasheet, PMA_CNT_BLK is no longer available
    and PM2_CNT_BLK should not be used.  Setup for these have been
    removed from the table and .h file.
    
    Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957
    Signed-off-by: Martin Roth <martin at se-eng.com>
---
 src/southbridge/amd/agesa/hudson/fadt.c   | 146 ++++++++++++++++++------------
 src/southbridge/amd/agesa/hudson/hudson.h |   2 -
 2 files changed, 88 insertions(+), 60 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c
index ee0334c..27b5600 100644
--- a/src/southbridge/amd/agesa/hudson/fadt.c
+++ b/src/southbridge/amd/agesa/hudson/fadt.c
@@ -28,6 +28,16 @@
 #include <device/device.h>
 #include "hudson.h"
 
+#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
+
+#ifndef FADT_PM_PROFILE
+	#define FADT_PM_PROFILE PM_UNSPECIFIED
+#endif
+
+/*
+ * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
+ * in the ACPI 3.0b specification.
+ */
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
@@ -37,24 +47,23 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
-	header->length = 244;
-	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = ACPI_FADT_REV_ACPI_3_0;
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 	header->asl_compiler_revision = 0;
 
 	fadt->firmware_ctrl = (u32) facs;
 	fadt->dsdt = (u32) dsdt;
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
-	fadt->preferred_pm_profile = 0x03;
-	fadt->sci_int = 9;
-	/* disable system management mode by setting to 0: */
-	fadt->smi_cmd = 0;
-	fadt->acpi_enable = 0xf0;
-	fadt->acpi_disable = 0xf1;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0xe2;
+	fadt->model = 0;		/* reserved, should be 0 ACPI 3.0 */
+	fadt->preferred_pm_profile = FADT_PM_PROFILE;
+	fadt->sci_int = 9;		/* HUDSON - IRQ 09 – ACPI SCI */
+	fadt->smi_cmd = 0;		/* disable system management mode */
+	fadt->acpi_enable = 0;	/* unused if SMI_CMD = 0 */
+	fadt->acpi_disable = 0;	/* unused if SMI_CMD = 0 */
+	fadt->s4bios_req = 0;	/* unused if SMI_CMD = 0 */
+	fadt->pstate_cnt = 0;	/* unused if SMI_CMD = 0 */
 
 	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
 	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
@@ -72,9 +81,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
 	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
 
-	pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
-	pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
-
 	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
 					* the contents of the PM registers at
 					* index 60-6B to decode ACPI I/O address.
@@ -85,100 +91,124 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->pm1b_evt_blk = 0x0000;
 	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
 	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+	fadt->pm2_cnt_blk = 0x0000;
 	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
 	fadt->gpe0_blk = ACPI_GPE0_BLK;
-	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+	fadt->gpe1_blk = 0x0000;		/* No gpe1 block in hudson */
 
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 8;
+	fadt->pm1_evt_len = 4;	/* 32 bits */
+	fadt->pm1_cnt_len = 2;	/* 16 bits */
+	fadt->pm2_cnt_len = 0;
+	fadt->pm_tmr_len = 4;	/* 32 bits */
+	fadt->gpe0_blk_len = 8;	/* 64 bits */
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
 
-	fadt->cst_cnt = 0xe3;
-	fadt->p_lvl2_lat = 101;
-	fadt->p_lvl3_lat = 1001;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 3;
+	fadt->cst_cnt = 0x00;	/* unused if SMI_CMD = 0 */
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;	/* set to 0 if WBINVD is 1 in flags */
+	fadt->flush_stride = 0;	/* set to 0 if WBINVD is 1 in flags */
+	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
+	fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
 	fadt->day_alrm = 0;	/* 0x7d these have to be */
 	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alrm work */
-	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
-	fadt->flags = 0x0001c1a5 | 1 << 10;/* 0x25; */
-
-	fadt->res2 = 0;
-
-	fadt->reset_reg.space_id = 1;
+	fadt->century = 0;	/* 0x7f to make rtc alarm work */
+	fadt->iapc_boot_arch = FADT_BOOT_ARCH;	/* See table 5-10 */
+	fadt->res2 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
+	fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
+				ACPI_FADT_C1_SUPPORTED |
+				ACPI_FADT_SLEEP_BUTTON |
+				ACPI_FADT_S4_RTC_WAKE |
+				ACPI_FADT_32BIT_TIMER |
+				ACPI_FADT_RESET_REGISTER |
+				ACPI_FADT_PCI_EXPRESS_WAKE |
+				ACPI_FADT_PLATFORM_CLOCK |
+				ACPI_FADT_S4_RTC_VALID |
+				ACPI_FADT_REMOTE_POWER_ON;
+
+	/* Format is from 5.2.3.1: Generic Address Structure */
+	/* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
+	/* 8 bit write of value 0x06 to 0xCF9 in IO space */
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->reset_reg.bit_width = 8;
 	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
 	fadt->reset_reg.addrl = 0xcf9;
 	fadt->reset_reg.addrh = 0x0;
 
 	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = (u32) facs;
+
+	fadt->res3 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
+	fadt->res4 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
+	fadt->res5 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
+
+	fadt->x_firmware_ctl_l = 0;	/* set to 0 if firmware_ctrl is used */
 	fadt->x_firmware_ctl_h = 0;
 	fadt->x_dsdt_l = (u32) dsdt;
 	fadt->x_dsdt_h = 0;
 
-	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm1a_evt_blk.bit_width = 32;
 	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
 	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
 	fadt->x_pm1a_evt_blk.addrh = 0x0;
 
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
 	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
 	fadt->x_pm1b_evt_blk.addrl = 0x0;
 	fadt->x_pm1b_evt_blk.addrh = 0x0;
 
-	fadt->x_pm1a_cnt_blk.space_id = 1;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm1a_cnt_blk.bit_width = 16;
 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.access_size = 0;
 	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
 
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
 
-	fadt->x_pm2_cnt_blk.space_id = 1;
+	/*
+	 * Note: Under this current AMD C state implementation, this is no longer
+	 *       used and should not be reported to OS.
+	 */
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm2_cnt_blk.bit_width = 0;
 	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = 0;
 	fadt->x_pm2_cnt_blk.addrh = 0x0;
 
-	fadt->x_pm_tmr_blk.space_id = 1;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm_tmr_blk.bit_width = 32;
 	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
 
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 32;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
 	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
 	fadt->x_gpe0_blk.addrh = 0x0;
 
-	fadt->x_gpe1_blk.space_id = 1;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_gpe1_blk.bit_width = 0;
 	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.access_size = 0;
 	fadt->x_gpe1_blk.addrl = 0;
 	fadt->x_gpe1_blk.addrh = 0x0;
 
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
index 15738aa..ef44874 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ b/src/southbridge/amd/agesa/hudson/hudson.h
@@ -35,7 +35,6 @@
 
 #define ACPI_PM_EVT_BLK		(HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
 #define ACPI_PM1_CNT_BLK	(HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK	(HUDSON_ACPI_IO_BASE + 0x0F) /* 1 byte, TODO: Is it 0xFE00? */
 #define ACPI_PM_TMR_BLK		(HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */
 #define ACPI_GPE0_BLK		(HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */
 #define ACPI_CPU_CONTROL	(HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */
@@ -55,7 +54,6 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
 #define CPU_CNT_BLK_ADDRESS                     0x810                           //      CpuControlBlkAddr;
 #define GPE0_BLK_ADDRESS                        0x820                           //  AcpiGpe0BlkAddr;
 #define SMI_CMD_PORT                            0xB0                            //      SmiCmdPortAddr;
-#define ACPI_PMA_CNT_BLK_ADDRESS        0xFE00                          //      AcpiPmaCntBlkAddr;
 #define SPIROM_BASE_ADDRESS_REGISTER    0xA0
 
 #ifdef __PRE_RAM__



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