[coreboot] New patch to review for coreboot: 60c90fd Move init.S to a proper filename

Ronald G. Minnich (rminnich@gmail.com) gerrit at coreboot.org
Sat Jan 12 00:08:22 CET 2013


Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2141

-gerrit

commit 60c90fd7f9a76f7ae09a74912d9960c8644eae4c
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Fri Jan 11 15:07:50 2013 -0800

    Move init.S to a proper filename
    
    Also, remove unnecessary junk and prepare for future build changes.
    
    Change-Id: I143777ec7e67ea4d6fed00084aafcb94c7866b4d
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
 src/arch/armv7/Makefile.inc  |  2 +-
 src/arch/armv7/bootblock.inc | 92 +++++++++++++++++++++++++++++++++++++++++++
 src/arch/armv7/init.S        | 93 --------------------------------------------
 3 files changed, 93 insertions(+), 94 deletions(-)

diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index d7fbbdf..e86e135 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -149,7 +149,7 @@ CFLAGS += \
 # For various headers imported from Linux
 CFLAGS += -D__LINUX_ARM_ARCH__=7
 
-crt0s = $(src)/arch/armv7/init.S
+crt0s = $(src)/arch/armv7/bootblock.inc
 ldscripts =
 ldscripts += $(src)/arch/armv7/romstage.ld
 
diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc
new file mode 100644
index 0000000..f76391b
--- /dev/null
+++ b/src/arch/armv7/bootblock.inc
@@ -0,0 +1,92 @@
+/*
+ * Early initialization code for ARMv7 architecture.
+ *
+ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
+ * U-Boot, which itself got the file from armboot.
+ *
+ * Copyright (c) 2004	Texas Instruments <r-woodruff2 at ti.com>
+ * Copyright (c) 2001	Marius Gröger <mag at sysgo.de>
+ * Copyright (c) 2002	Alex Züpke <azu at sysgo.de>
+ * Copyright (c) 2002	Gary Jennejohn <garyj at denx.de>
+ * Copyright (c) 2003	Richard Woodruff <r-woodruff2 at ti.com>
+ * Copyright (c) 2003	Kshitij <kshitij at ti.com>
+ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim at ti.com>
+ * Copyright (c) 2013   The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <system.h>
+
+_bl1:
+	/* For now we have to live with a first stage boot loader
+	 * on ARM, which is 8KB in size and it is prepended to the
+	 * reset vector
+	 */
+	/* this comes a bit later. */
+//	.skip 8192
+
+.globl _start
+_start: b	reset
+	.balignl 16,0xdeadbeef
+
+_cbfs_master_header:
+	/* The CBFS master header is inserted here by cbfstool
+	 * when coreboot.rom is being created. Hence, we leave
+	 * some space for it.
+	 */
+	.skip 64
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0, cpsr
+	bic	r0, r0, #0x1f
+	orr	r0, r0, #0xd3
+	msr	cpsr,r0
+
+	/*
+	 * From Cortex-A Series Programmer's Guide:
+	 * Only CPU 0 performs initialization. Other CPUs go into WFI
+	 * to do this, first work out which CPU this is
+	 * this code typically is run before any other initialization step
+	 */
+	mrc p15, 0, r1, c0, c0, 5	@ Read Multiprocessor Affinity Register
+	and r1, r1, #0x3 @ Extract CPU ID bits
+	cmp r1, #0
+	bne wait_for_interrupt		@ If this is not core0, wait
+
+/* Set stackpointer in internal RAM to call board_init_f */
+call_bootblock:
+	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR) /* Set up stack pointer */
+	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
+	ldr	r0,=0x00000000
+	/*
+	 * Use "bl" instead of "b" even though we do not intend to return.
+	 * "bl" gets compiled to "blx" if we're transitioning from ARM to
+	 * Thumb. However, "b" will not and GCC may attempt to create a
+	 * wrapper which is currently broken.
+	 */
+	/* for now call board_init_f; change later. We're trying to get as much into ToT as
+	 * we can
+	 */
+	bl	board_init_f
+	bl	main
+
+wait_for_interrupt:
+	wfi
+	mov	pc, lr			@ back to my caller
diff --git a/src/arch/armv7/init.S b/src/arch/armv7/init.S
deleted file mode 100644
index 7848581..0000000
--- a/src/arch/armv7/init.S
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Early initialization code for ARMv7 architecture.
- *
- * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
- * U-Boot, which itself got the file from armboot.
- *
- * Copyright (c) 2004	Texas Instruments <r-woodruff2 at ti.com>
- * Copyright (c) 2001	Marius Gröger <mag at sysgo.de>
- * Copyright (c) 2002	Alex Züpke <azu at sysgo.de>
- * Copyright (c) 2002	Gary Jennejohn <garyj at denx.de>
- * Copyright (c) 2003	Richard Woodruff <r-woodruff2 at ti.com>
- * Copyright (c) 2003	Kshitij <kshitij at ti.com>
- * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim at ti.com>
- * Copyright (c) 2013   The Chromium OS Authors
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <system.h>
-
-.globl _start
-_start: b	reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-_undefined_instruction: .word _undefined_instruction
-_software_interrupt:	.word _software_interrupt
-_prefetch_abort:	.word _prefetch_abort
-_data_abort:		.word _data_abort
-_not_used:		.word _not_used
-_irq:			.word _irq
-_fiq:			.word _fiq
-_pad:			.word 0x12345678 /* now 16*4=64 */
-
-	.balignl 16,0xdeadbeef
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x1f
-	orr	r0, r0, #0xd3
-	msr	cpsr,r0
-
-	/*
-	 * From Cortex-A Series Programmer's Guide:
-	 * Only CPU 0 performs initialization. Other CPUs go into WFI
-	 * to do this, first work out which CPU this is
-	 * this code typically is run before any other initialization step
-	 */
-	mrc p15, 0, r1, c0, c0, 5	@ Read Multiprocessor Affinity Register
-	and r1, r1, #0x3 @ Extract CPU ID bits
-	cmp r1, #0
-	bne wait_for_interrupt		@ If this is not core0, wait
-
-	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
-	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
-	bic	r0, #CR_V		@ V = 0
-	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register
-
-	/* Set vector address in CP15 VBAR register */
-	ldr	r0, =_start
-	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	mov	sp, r0
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-wait_for_interrupt:
-	wfi
-	mov	pc, lr			@ back to my caller



More information about the coreboot mailing list