[coreboot] Patch set updated for coreboot: 44b4399 ARM bootblock approach (incomplete)

David Hendricks (dhendrix@chromium.org) gerrit at coreboot.org
Fri Jan 11 03:49:19 CET 2013


David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2118

-gerrit

commit 44b43994c9526f7f726eb20bb4dfc00bb8390eca
Author: David Hendricks <dhendrix at chromium.org>
Date:   Tue Jan 8 21:05:06 2013 -0800

    ARM bootblock approach (incomplete)
    
    Do not attempt to commit, just making this available so it doesn't get lost
    
    Change-Id: I9cc2a8191d2db38b27b6363ba673e5a360de9684
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/arch/armv7/Makefile.inc               | 26 ++++-----
 src/arch/armv7/bootblock.inc              | 87 +++++++++++++++++++++++++++++
 src/arch/armv7/bootblock.lds              | 49 ++++++++++++++++
 src/arch/armv7/bootblock_simple.c         | 34 ++++++-----
 src/arch/armv7/include/arch/cbfs.h        | 68 ++++++++++++++++++++++
 src/arch/armv7/include/bootblock_common.h | 71 +++--------------------
 src/arch/armv7/init.S                     | 93 -------------------------------
 src/arch/armv7/lib/id.lds                 |  2 +-
 src/cpu/samsung/exynos5250/Kconfig        | 12 +++-
 9 files changed, 250 insertions(+), 192 deletions(-)

diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index d7fbbdf..57a5a50 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -49,7 +49,7 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL)
 	$(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \
 		-B $(objcbfs)/bootblock.bin -a 64 \
-		-o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) ))
+		-o $(CONFIG_BOOTBLOCK_OFFSET)
 	$(prebuild-files) true
 	mv $@.tmp $@
 else
@@ -149,7 +149,6 @@ CFLAGS += \
 # For various headers imported from Linux
 CFLAGS += -D__LINUX_ARM_ARCH__=7
 
-crt0s = $(src)/arch/armv7/init.S
 ldscripts =
 ldscripts += $(src)/arch/armv7/romstage.ld
 
@@ -223,19 +222,14 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL
 ################################################################################
 # Build the bootblock
 
-#bootblock_lds = $(src)/arch/armv7/ldscript_fallback_cbfs.lb
-bootblock_lds = $(src)/arch/armv7/lib/id.lds
-#bootblock_lds = $(src)/arch/armv7/romstage.ld
+bootblock_lds = $(src)/arch/armv7/bootblock.lds
+bootblock_lds += $(src)/arch/armv7/lib/id.lds
 bootblock_lds += $(chipset_bootblock_lds)
 
+bootblock_inc += $(src)/arch/armv7/bootblock.inc
 bootblock_inc += $(src)/arch/armv7/lib/id.inc
 bootblock_inc += $(chipset_bootblock_inc)
-
-# FIXME: CONFIG_NEON or something similar for ARM?
-#ifeq ($(CONFIG_SSE),y)
-#bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-#endif
-#bootblock_inc += $(objgenerated)/bootblock.inc
+bootblock_inc += $(objgenerated)/bootblock.inc
 
 $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -253,11 +247,11 @@ $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(o
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
 
-#$(objgenerated)/bootblock.inc: $(src)/arch/armv7/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
-#	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
-#	$(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \
-#		$< > $(objgenerated)/bootblock.inc.d
-#	$(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@
+$(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(OPTION_TABLE_H)
+	@printf "    CC      $(subst $(obj)/,,$(@))\n"
+	$(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \
+		$< > $(objgenerated)/bootblock.inc.d
+	$(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@
 
 $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc
new file mode 100644
index 0000000..90850d6
--- /dev/null
+++ b/src/arch/armv7/bootblock.inc
@@ -0,0 +1,87 @@
+/*
+ * Early initialization code for ARMv7 architecture.
+ *
+ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
+ * U-Boot, which itself got the file from armboot.
+ *
+ * Copyright (c) 2004	Texas Instruments <r-woodruff2 at ti.com>
+ * Copyright (c) 2001	Marius Gröger <mag at sysgo.de>
+ * Copyright (c) 2002	Alex Züpke <azu at sysgo.de>
+ * Copyright (c) 2002	Gary Jennejohn <garyj at denx.de>
+ * Copyright (c) 2003	Richard Woodruff <r-woodruff2 at ti.com>
+ * Copyright (c) 2003	Kshitij <kshitij at ti.com>
+ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim at ti.com>
+ * Copyright (c) 2013   The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <system.h>
+
+_bl1:
+	/* For now we have to live with a first stage boot loader
+	 * on ARM, which is 8KB in size and it is prepended to the
+	 * reset vector
+	 */
+	.skip 8192
+
+.globl _start
+_start: b	reset
+	.balignl 16,0xdeadbeef
+
+_cbfs_master_header:
+	/* The CBFS master header is inserted here by cbfstool
+	 * when coreboot.rom is being created. Hence, we leave
+	 * some space for it.
+	 */
+	.skip 64
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0, cpsr
+	bic	r0, r0, #0x1f
+	orr	r0, r0, #0xd3
+	msr	cpsr,r0
+
+	/*
+	 * From Cortex-A Series Programmer's Guide:
+	 * Only CPU 0 performs initialization. Other CPUs go into WFI
+	 * to do this, first work out which CPU this is
+	 * this code typically is run before any other initialization step
+	 */
+	mrc p15, 0, r1, c0, c0, 5	@ Read Multiprocessor Affinity Register
+	and r1, r1, #0x3 @ Extract CPU ID bits
+	cmp r1, #0
+	bne wait_for_interrupt		@ If this is not core0, wait
+
+/* Set stackpointer in internal RAM to call board_init_f */
+call_bootblock:
+	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR) /* Set up stack pointer */
+	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
+	ldr	r0,=0x00000000
+	/*
+	 * Use "bl" instead of "b" even though we do not intend to return.
+	 * "bl" gets compiled to "blx" if we're transitioning from ARM to
+	 * Thumb. However, "b" will not and GCC may attempt to create a
+	 * wrapper which is currently broken.
+	 */
+	bl	main
+
+wait_for_interrupt:
+	wfi
+	mov	pc, lr			@ back to my caller
diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds
new file mode 100644
index 0000000..90e37a0
--- /dev/null
+++ b/src/arch/armv7/bootblock.lds
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+TARGET(binary)
+SECTIONS
+{
+	ROMLOC = 0x2023400 - 8192;
+
+	/* This section might be better named .setup */
+	.rom ROMLOC : {
+		_rom = .;
+		*(.text);
+		*(.text.*);
+		*(.rom.text);
+		*(.rom.data);
+		*(.rom.data.*);
+		*(.rodata.*);
+		_erom = .;
+	} = 0xff
+
+	/DISCARD/ : {
+		*(.comment)
+		*(.note)
+		*(.comment.*)
+		*(.note.*)
+		*(.ARM.*)
+	}
+}
diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c
index f447a29..c10ee1f 100644
--- a/src/arch/armv7/bootblock_simple.c
+++ b/src/arch/armv7/bootblock_simple.c
@@ -19,33 +19,31 @@
  * MA 02110-1301 USA
  */
 
-
-
 #include <bootblock_common.h>
+#include <arch/cbfs.h>
+#include <arch/hlt.h>
 
-
-#include "../../lib/uart8250.c"
-#include "lib/div.c"
-
-struct uart8250 uart = {
-	115200
-}; 
+static int boot_cpu(void)
+{
+	/*
+	 * FIXME: This is a stub for now. All non-boot CPUs should be
+	 * waiting for an interrupt. We could move the chunk of assembly
+	 * which puts them to sleep in here...
+	 */
+	return 1;
+}
 
 void main(unsigned long bist)
 {
-	init_uart8250(CONFIG_TTYS0_BASE, &uart);
-	uart8250_tx_byte(CONFIG_TTYS0_BASE, '@');
+	const char *target1 = "fallback/romstage";
+	unsigned long entry;
 
 	if (boot_cpu()) {
-		bootblock_cpu_init();
-		bootblock_northbridge_init();
-		bootblock_southbridge_init();
+		bootblock_mainboard_init();
 	}
-	const char* target1 = "fallback/romstage";
-	unsigned long entry;
+
 	entry = findstage(target1);
-	if (entry) call(entry, bist);
+	if (entry) call(entry);
 
 	hlt();
 }
-
diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h
new file mode 100644
index 0000000..afcfa6a
--- /dev/null
+++ b/src/arch/armv7/include/arch/cbfs.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __INCLUDE_ARCH_CBFS__
+#define __INCLUDE_ARCH_CBFS__
+
+#include <string.h>
+#include <types.h>
+#include <cbfs_core.h>
+#include <arch/byteorder.h>
+#include <arch/cbfs.h>
+
+static int cbfs_check_magic(struct cbfs_file *file)
+{
+	return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0;
+}
+
+static unsigned long findstage(const char* target)
+{
+	unsigned long offset;
+	void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR);
+	struct cbfs_header *header = (struct cbfs_header *) ptr;
+	// if (ntohl(header->magic) != CBFS_HEADER_MAGIC)
+	// 	printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n");
+
+	/* FIXME(dhendrix,reinauer): should this be ntohl(header->offset)? */
+	offset = 0 - ntohl(header->romsize) + ntohl(header->offset);
+	int align = ntohl(header->align);
+	while(1) {
+		struct cbfs_file *file = (struct cbfs_file *) offset;
+		if (!cbfs_check_magic(file))
+			return 0;
+		if (!strcmp(CBFS_NAME(file), target))
+			return (unsigned long)CBFS_SUBHEADER(file);
+		int flen = ntohl(file->len);
+		int foffset = ntohl(file->offset);
+		unsigned long oldoffset = offset;
+		offset = ALIGN(offset + foffset + flen, align);
+		if (offset <= oldoffset)
+			return 0;
+		/* FIXME(dhendrix,reinauer): calculate the limit correctly */
+		if (offset < 0xFFFFFFFF - ntohl(header->romsize))
+			return 0;
+	}
+}
+
+static inline void call(unsigned long addr)
+{
+	void (*doit)(void) = (void *)addr;
+	doit();
+}
+#endif
diff --git a/src/arch/armv7/include/bootblock_common.h b/src/arch/armv7/include/bootblock_common.h
index f5c7129..39af453 100644
--- a/src/arch/armv7/include/bootblock_common.h
+++ b/src/arch/armv7/include/bootblock_common.h
@@ -1,69 +1,14 @@
-#include <types.h>
-#include <cbfs.h>
-#include <string.h>
-#include <arch/byteorder.h>
-
-
-#define boot_cpu(x) 1
-
 #ifdef CONFIG_BOOTBLOCK_CPU_INIT
 #include CONFIG_BOOTBLOCK_CPU_INIT
-#else
-static void bootblock_cpu_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#else
-static void bootblock_northbridge_init(void) { }
 #endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#else
-static void bootblock_southbridge_init(void) { }
-#endif
-
-static int cbfs_check_magic(struct cbfs_file *file)
-{
-	return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0;
-}
-
-static unsigned long findstage(const char* target)
-{
-	unsigned long offset;
-
-	void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR);
-	struct cbfs_header *header = (struct cbfs_header *) ptr;
-	// if (ntohl(header->magic) != CBFS_HEADER_MAGIC)
-	// 	printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n");
-
-	offset = 0 - ntohl(header->romsize) + ntohl(header->offset);
-	int align = ntohl(header->align);
-	while(1) {
-		struct cbfs_file *file = (struct cbfs_file *) offset;
-		if (!cbfs_check_magic(file))
-			return 0;
-		if (!strcmp(CBFS_NAME(file), target))
-			return (unsigned long)CBFS_SUBHEADER(file);
-		int flen = ntohl(file->len);
-		int foffset = ntohl(file->offset);
-		unsigned long oldoffset = offset;
-		offset = ALIGN(offset + foffset + flen, align);
-		if (offset <= oldoffset)
-			return 0;
-		if (offset < 0xFFFFFFFF - ntohl(header->romsize))
-			return 0;
-	}
-}
-
-
-static void call(unsigned long addr, unsigned long bist)
-{
-	asm volatile ("mov r0, %1\nbx %0\n" : : "r" (addr), "r" (bist));
-}
 
-static void hlt(void)
+#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT
+#include CONFIG_BOOTBLOCK_MAINBOARD_INIT
+#else
+static void bootblock_mainboard_init(void)
 {
-	/* is there such a thing as hlt on ARM? */
-	// asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
-	asm volatile ("1:\nb 1b\n\t");
+#ifdef CONFIG_BOOTBLOCK_CPU_INIT
+	bootblock_cpu_init();
+#endif
 }
+#endif
diff --git a/src/arch/armv7/init.S b/src/arch/armv7/init.S
deleted file mode 100644
index 7848581..0000000
--- a/src/arch/armv7/init.S
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Early initialization code for ARMv7 architecture.
- *
- * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
- * U-Boot, which itself got the file from armboot.
- *
- * Copyright (c) 2004	Texas Instruments <r-woodruff2 at ti.com>
- * Copyright (c) 2001	Marius Gröger <mag at sysgo.de>
- * Copyright (c) 2002	Alex Züpke <azu at sysgo.de>
- * Copyright (c) 2002	Gary Jennejohn <garyj at denx.de>
- * Copyright (c) 2003	Richard Woodruff <r-woodruff2 at ti.com>
- * Copyright (c) 2003	Kshitij <kshitij at ti.com>
- * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim at ti.com>
- * Copyright (c) 2013   The Chromium OS Authors
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <system.h>
-
-.globl _start
-_start: b	reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-_undefined_instruction: .word _undefined_instruction
-_software_interrupt:	.word _software_interrupt
-_prefetch_abort:	.word _prefetch_abort
-_data_abort:		.word _data_abort
-_not_used:		.word _not_used
-_irq:			.word _irq
-_fiq:			.word _fiq
-_pad:			.word 0x12345678 /* now 16*4=64 */
-
-	.balignl 16,0xdeadbeef
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x1f
-	orr	r0, r0, #0xd3
-	msr	cpsr,r0
-
-	/*
-	 * From Cortex-A Series Programmer's Guide:
-	 * Only CPU 0 performs initialization. Other CPUs go into WFI
-	 * to do this, first work out which CPU this is
-	 * this code typically is run before any other initialization step
-	 */
-	mrc p15, 0, r1, c0, c0, 5	@ Read Multiprocessor Affinity Register
-	and r1, r1, #0x3 @ Extract CPU ID bits
-	cmp r1, #0
-	bne wait_for_interrupt		@ If this is not core0, wait
-
-	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
-	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
-	bic	r0, #CR_V		@ V = 0
-	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register
-
-	/* Set vector address in CP15 VBAR register */
-	ldr	r0, =_start
-	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	mov	sp, r0
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-wait_for_interrupt:
-	wfi
-	mov	pc, lr			@ back to my caller
diff --git a/src/arch/armv7/lib/id.lds b/src/arch/armv7/lib/id.lds
index 9e31ee6..22b4a02 100644
--- a/src/arch/armv7/lib/id.lds
+++ b/src/arch/armv7/lib/id.lds
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (0x100000000 - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start);
+	. = (0x2024000) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index 360c57f..a334b63 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -1,10 +1,20 @@
+# FIXME: shouldn't this be 0x3400? Or maybe the bootblock in ROM needs
+# to follow the BL1 image, but in SRAM it needs to be at 0x3400? Hm...
 config BOOTBLOCK_OFFSET
 	hex "Bootblock offset"
-	default 0x3400
+	default 0x2000
 	help
 	  This is where the Coreboot bootblock resides. For Exynos5250,
 	  this value is pre-determined by the vendor-provided BL1.
 
+config BOOTBLOCK_CPU_INIT
+	bool
+	default n
+	help
+	  Run CPU/SoC-specific bootblock code. This is useful if the
+	  bootblock must load microcode or copy data from ROM before
+	  searching for the bootblock.
+
 config EXYNOS_ACE_SHA
 	bool
 	default n



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