[coreboot] New patch to review for coreboot: 535a8af snow: Stuff to support building image with BL1

[David Hendricks (dhendrix@chromium.org)]

David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2093

-gerrit

commit 535a8af278eb17bbfe1770d067912c0adca67d4d
Author: David Hendricks <dhendrix at chromium.org>
Date:   Wed Jan 2 17:41:51 2013 -0800

    snow: Stuff to support building image with BL1
    
    This patch does two things which will take effect in follow-up
    patches:
    1. Add an intermediate Makefile rule for dd'ing BL1 into the
       coreboot.rom pre-image. This is modeled after a similar hack
       for the bd82x6x southbridge.
    2. Add a Kconfig variable, BOOTBLOCK_OFFSET, which will be used to
       pass the bootblock offset into cbfstool.
    
    Change-Id: I89da255dc903c387b754b06a11bb3439035ead87
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/cpu/samsung/exynos5250/Kconfig      |  7 +++++++
 src/cpu/samsung/exynos5250/Makefile.inc | 10 ++++++++++
 2 files changed, 17 insertions(+)

diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index c2d9b9f..360c57f 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -1,3 +1,10 @@
+config BOOTBLOCK_OFFSET
+	hex "Bootblock offset"
+	default 0x3400
+	help
+	  This is where the Coreboot bootblock resides. For Exynos5250,
+	  this value is pre-determined by the vendor-provided BL1.
+
 config EXYNOS_ACE_SHA
 	bool
 	default n
diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc
index 556631a..1ff2327 100644
--- a/src/cpu/samsung/exynos5250/Makefile.inc
+++ b/src/cpu/samsung/exynos5250/Makefile.inc
@@ -1,3 +1,8 @@
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+INTERMEDIATE += exynos5250_add_bl1
+
 romstage-y += clock.c
 romstage-y += clock_init.c
 romstage-y += exynos_cache.c
@@ -30,3 +35,8 @@ ramstage-y += uart.c
 ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c
 ramstage-$(CONFIG_SPL_BUILD) += dmc_common.c
 ramstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c
+
+exynos5250_add_bl1: $(obj)/coreboot.pre
+	printf "    DD         Adding Samsung Exynos5250 BL1\n"
+	dd if=3rdparty/cpu/samsung/exynos5250/E5250.nbl1.bin \
+		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1