[coreboot] New patch to review for coreboot: 1d78246 Fix socket LGA775
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Feb 26 12:57:22 CET 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2525
-gerrit
commit 1d7824607872837714e340631a26a25c0f159434
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Feb 26 13:49:56 2013 +0200
Fix socket LGA775
Models 6ex and 6fx select UDELAY_LAPIC so cannot select
contradicting UDELAY_TSC here.
Model 1067x requires speedstep.
Change-Id: I69d3ec8085912dfbe5fe31c81fa0a437228fa48f
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/socket_LGA775/Kconfig | 1 -
src/cpu/intel/socket_LGA775/Makefile.inc | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index dfb3181..e5c687a 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -14,7 +14,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_MODEL_1067X
select MMX
select SSE
- select UDELAY_TSC
select SIPI_VECTOR_IN_ROM
config DCACHE_RAM_SIZE
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index 100b4d8..ea68ab1 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -13,5 +13,6 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
+subdirs-y += ../speedstep
cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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