[coreboot] Patch merged into coreboot/master: a96d24d AMD Southbridge: Add RTC init to lpc_init

gerrit at coreboot.org gerrit at coreboot.org
Mon Feb 25 19:28:44 CET 2013

the following patch was just integrated into master:
commit a96d24d672abfd2ce91caa2d762fdce3d67da600
Author: Mike Loptien <mike.loptien at se-eng.com>
Date:   Mon Feb 25 10:41:28 2013 -0700

    AMD Southbridge: Add RTC init to lpc_init
    Adding RTC init code to the Southbridge initialization
    code in 'lpc_init'.  This initializes the RTC so that the
    Date Alarm register is set to a valid value (0x00) at
    startup.  By setting the Date Alarm register to 0x00,
    it does not get evaluated along with the seconds,
    minutes, and hours when running 'fwts s3'.
    Information about fwts (Firmware Test Suite) can be
    found here:
    This is the same edit made to the CIMX SB800 titled
    'AMD/Persimmon: Add RTC init to CIMX SB800' with commit
    ID: c4d3d which can be viewed here:
    Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90
    Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
    Reviewed-on: http://review.coreboot.org/2510
    Reviewed-by: Martin Roth <martin.roth at se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin at se-eng.com>

Build-Tested: build bot (Jenkins) at Mon Feb 25 19:08:10 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Mon Feb 25 19:05:24 2013, giving +2
Reviewed-By: Martin Roth <martin.roth at se-eng.com> at Mon Feb 25 19:02:14 2013, giving +1
Reviewed-By: Dave Frodin <dave.frodin at se-eng.com> at Mon Feb 25 19:28:43 2013, giving +2
See http://review.coreboot.org/2510 for details.


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