[coreboot] New patch to review for coreboot: 2a14e8e AMD Southbridge: Add RTC init to lpc_init

[Mike Loptien (mike.loptien@se-eng.com)]

Mike Loptien (mike.loptien at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2510

-gerrit

commit 2a14e8e643564d4762d81b6c0444037842f834d2
Author: Mike Loptien <mike.loptien at se-eng.com>
Date:   Mon Feb 25 10:41:28 2013 -0700

    AMD Southbridge: Add RTC init to lpc_init
    
    Adding RTC init code to the Southbridge initialization
    code in 'lpc_init'.  This initializes the RTC so that the
    Date Alarm register is set to a valid value (0x00) at
    startup.  By setting the Date Alarm register to 0x00,
    it does not get evaluated along with the seconds,
    minutes, and hours when running 'fwts s3'.
    Information about fwts (Firmware Test Suite) can be
    found here:
    https://wiki.ubuntu.com/Kernel/Reference/fwts
    
    This is the same edit made to the CIMX SB800 titled
    'AMD/Persimmon: Add RTC init to CIMX SB800' with commit
    ID: c4d3d which can be viewed here:
    http://review.coreboot.org/#/c/2488/
    
    Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90
    Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
---
 src/southbridge/amd/agesa/hudson/lpc.c | 7 +++++++
 src/southbridge/amd/cimx/sb700/late.c  | 7 +++++++
 src/southbridge/amd/cimx/sb900/late.c  | 7 +++++++
 3 files changed, 21 insertions(+)

diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 86e937e..aad4eb9 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -69,6 +69,13 @@ static void lpc_init(device_t dev)
 	pci_write_config8(dev, 0xBB, byte);
 
 	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+
+	/* Initialize the real time clock.
+	 * The 0 argument tells rtc_init not to
+	 * update CMOS unless it is invalid.
+	 * 1 tells rtc_init to always initialize the CMOS.
+	 */
+	rtc_init(0);
 }
 
 static void hudson_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index be2b8cd..4c5dde9 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -79,6 +79,13 @@ static void lpc_init(device_t dev)
 
 	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
 
+	/* Initialize the real time clock.
+	 * The 0 argument tells rtc_init not to
+	 * update CMOS unless it is invalid.
+	 * 1 tells rtc_init to always initialize the CMOS.
+	 */
+	rtc_init(0);
+
 	printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n");
 }
 
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 85485ed..65cea69 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -101,6 +101,13 @@ static void lpc_init(device_t dev)
 //-	hpetInit(sb_config, &(sb_config->BuildParameters));
 	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
 
+	/* Initialize the real time clock.
+	 * The 0 argument tells rtc_init not to
+	 * update CMOS unless it is invalid.
+	 * 1 tells rtc_init to always initialize the CMOS.
+	 */
+	rtc_init(0);
+
 	printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n");
 }