[coreboot] Patch merged into coreboot/master: ac529b1 AMD/Persimmon: Add RTC init to CIMX SB800

gerrit at coreboot.org gerrit at coreboot.org
Sat Feb 23 01:16:51 CET 2013

the following patch was just integrated into master:
commit ac529b1e15a2872b6e2894b0661fb49b11c95169
Author: Mike Loptien <mike.loptien at se-eng.com>
Date:   Fri Feb 22 13:18:31 2013 -0700

    AMD/Persimmon: Add RTC init to CIMX SB800
    Adding RTC init code to the Southbridge initialization
    code in 'late.c'.  This initializes the RTC so that the
    Date Alarm register is set to a valid value (0x00) at
    startup.  By setting the Date Alarm register to 0x00,
    it does not get evaluated along with the seconds,
    minutes, and hours when running 'fwts s3'.
    Information about fwts (Firmware Test Suite) can be
    found here:
    This was tested on a Persimmon but will apply to
    other mainboards as well.
    Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4
    Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
    Reviewed-on: http://review.coreboot.org/2488
    Reviewed-by: Dave Frodin <dave.frodin at se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Fri Feb 22 23:36:37 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Sat Feb 23 01:16:50 2013, giving +2
See http://review.coreboot.org/2488 for details.


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