[coreboot] Patch merged into coreboot/master: 384ee9f Persimmon: drop useless DDR3 voltage code copied from Inagua

gerrit at coreboot.org gerrit at coreboot.org
Mon Feb 18 22:50:01 CET 2013

the following patch was just integrated into master:
commit 384ee9f1429db8543724e868b7ffd5fc7e2aa915
Author: Jens Rottmann <JRottmann at LiPPERTembedded.de>
Date:   Mon Feb 18 20:26:50 2013 +0100

    Persimmon: drop useless DDR3 voltage code copied from Inagua
    Inagua can use GPIOs 178,179 to switch VMEM to 1.5, 1.35 or 1.25 V,
    which it does according to data read from the SO-DIMM's SPD EEPROM.
    On Persimmon (according to DB-FT1 rev. D schematics) both GPIOs are
    unconnected, there is no way to change the 1.5 V DDR3 voltage (save
    unsoldering a resistor). The whole code copied over from Inagua is
    Removed the code, instead a comment hints at Inagua, for people who do designs
    based on Persimmon but do have a way to change VMEM.
    The line ...->DDR3Voltage = VOLT1_5; is supposed to make the AGESA DDR3 code
    select the RAM timings for the actually supplied voltage instead of the
    hoped-for but unavailable lower voltage. I have no idea how to test this, but
    in any case it can't hurt.
    Change-Id: Id098e09418b665645814a6ee2d41a3bff72238ba
    Signed-off-by: Jens Rottmann <JRottmann at LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2448
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter at stuge.se>

Build-Tested: build bot (Jenkins) at Mon Feb 18 20:57:47 2013, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Mon Feb 18 22:49:59 2013, giving +2
See http://review.coreboot.org/2448 for details.


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