[coreboot] Patch set updated for coreboot: 5696e9d snow: Set up MMU after DRAM is working

David Hendricks (dhendrix@chromium.org) gerrit at coreboot.org
Thu Feb 14 05:29:03 CET 2013

David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2379


commit 5696e9df858e0969d3ea0aa4aa8b3b3e9a43bbb5
Author: David Hendricks <dhendrix at chromium.org>
Date:   Tue Feb 12 15:37:12 2013 -0800

    snow: Set up MMU after DRAM is working
    This was omitted earlier while we were debugging DRAM code (0a5bc7f).
    It was likely broken due to inconsistent units earlier on. Now that
    things are cleaned up and working, let's add it back in.
    Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
 src/mainboard/google/snow/romstage.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 719337b..f6f858c 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -85,6 +85,8 @@ void main(void)
 	printk(BIOS_INFO, "ddr3_init done\n");
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
 	printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);

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