[coreboot] Patch set updated for coreboot: abb6747 Intel: Replace MSR 0xcd with MSR_FSB_FREQ
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Sun Feb 10 09:01:20 CET 2013
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2339
-gerrit
commit abb6747f7a46698f055bd9debead3e3cd6928e0d
Author: Patrick Georgi <patrick at georgi-clan.de>
Date: Sat Feb 9 15:56:04 2013 +0100
Intel: Replace MSR 0xcd with MSR_FSB_FREQ
And move the corresponding #define to speedstep.h
Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
src/cpu/intel/model_1067x/model_1067x_init.c | 1 -
src/cpu/intel/speedstep/acpi.c | 2 +-
src/cpu/x86/lapic/apic_timer.c | 5 +++--
src/include/cpu/intel/speedstep.h | 3 +++
src/northbridge/intel/gm45/delay.c | 3 ++-
src/northbridge/intel/i3100/raminit.c | 3 ++-
src/northbridge/intel/i3100/raminit_ep80579.c | 5 +++--
src/northbridge/intel/i5000/raminit.c | 3 ++-
src/northbridge/intel/i5000/udelay.c | 3 ++-
src/northbridge/intel/i945/udelay.c | 3 ++-
10 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index e81a6a7..c821474 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -99,7 +99,6 @@ static void enable_vmx(void)
}
#define MSR_BBL_CR_CTL3 0x11e
-#define MSR_FSB_FREQ 0xcd
static void configure_c_states(const int quad)
{
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 910055d..dfcc82e 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -67,7 +67,7 @@ static int determine_total_number_of_cores(void)
*/
static int get_fsb(void)
{
- const u32 fsbcode = rdmsr(0xcd).lo & 7;
+ const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
switch (fsbcode) {
case 0: return 800; /* / 3 == 266 */
case 1: return 400; /* / 3 == 133 */
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 53209fb..93e948f 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -25,6 +25,7 @@
#include <cpu/x86/car.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
+#include <cpu/intel/speedstep.h>
/* NOTE: This code uses global variables, so it can not be used during
* memory init.
@@ -53,11 +54,11 @@ static int set_timer_fsb(void)
switch (c.x86_model) {
case 0xe: /* Core Solo/Duo */
case 0x1c: /* Atom */
- timer_fsb = core_fsb[rdmsr(0xcd).lo & 7];
+ timer_fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
break;
case 0xf: /* Core 2 or Xeon */
case 0x17: /* Enhanced Core */
- timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
+ timer_fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
break;
case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 86778b1..f4c4d72 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -45,6 +45,7 @@
#define IA32_PERF_CTL 0x199
#define MSR_THERM2_CTL 0x19D
#define IA32_MISC_ENABLES 0x1A0
+#define MSR_FSB_FREQ 0xcd
#define MSR_FSB_CLOCK_VCC 0xce
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_BASE_ADDR 0xe3
@@ -104,7 +105,9 @@ typedef struct {
int num_states;
} sst_table_t;
+#ifndef __ROMCC__
void speedstep_gen_pstates(sst_table_t *);
+#endif
#define SPEEDSTEP_MAX_POWER_YONAH 31000
#define SPEEDSTEP_MIN_POWER_YONAH 13100
diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c
index 50bea2c..c33bbe2 100644
--- a/src/northbridge/intel/gm45/delay.c
+++ b/src/northbridge/intel/gm45/delay.c
@@ -21,6 +21,7 @@
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
#include "delay.h"
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
@@ -45,7 +46,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total)
u32 fsb = 0, divisor;
u32 d; /* ticks per us */
- msr = rdmsr(0xcd);
+ msr = rdmsr(MSR_FSB_FREQ);
switch (msr.lo & 0x07) {
case 5:
fsb = 400;
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index b453e8b..fa42efc 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -21,6 +21,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <cpu/intel/speedstep.h>
#include <stdlib.h>
#include "raminit.h"
#include "i3100.h"
@@ -583,7 +584,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
drc |= (1 << 4); /* independent clocks */
/* set front side bus speed */
- msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
+ msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */
value = msr.lo & 0x07;
drc &= ~(3 << 2);
drc |= (fsb_conversion[value] << 2);
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 5fe206f..4c688d5 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -20,6 +20,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <cpu/intel/speedstep.h>
#include "raminit_ep80579.h"
#include "ep80579.h"
@@ -441,8 +442,8 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
/* TODO check: */
/* set front side bus speed */
- msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
- print_debug("msr 0xcd = ");
+ msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */
+ print_debug("MSR FSB_FREQ(0xcd) = ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index ffc579a..3c913cf 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -25,6 +25,7 @@
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
+#include <cpu/intel/speedstep.h>
#include <console/console.h>
#include <spd.h>
#include <types.h>
@@ -1560,7 +1561,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
return 1;
}
- msr = rdmsr(0xcd);
+ msr = rdmsr(MSR_FSB_FREQ);
switch(msr.lo & 7) {
case 1:
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c
index 6462fe0..ff2da6f 100644
--- a/src/northbridge/intel/i5000/udelay.c
+++ b/src/northbridge/intel/i5000/udelay.c
@@ -21,6 +21,7 @@
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
#include <console/console.h>
/**
* Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
@@ -35,7 +36,7 @@ void udelay(u32 us)
u32 d; /* ticks per us */
u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */
- msr = rdmsr(0xcd);
+ msr = rdmsr(MSR_FSB_FREQ);
switch (msr.lo & 0x07) {
case 5:
fsb = 400;
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index ce5e9d8..be56008 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -22,6 +22,7 @@
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
@@ -46,7 +47,7 @@ void udelay(u32 us)
u32 fsb = 0, divisor;
u32 d; /* ticks per us */
- msr = rdmsr(0xcd);
+ msr = rdmsr(MSR_FSB_FREQ);
switch (msr.lo & 0x07) {
case 5:
fsb = 400;
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