[coreboot] Patch merged into coreboot/master: 0f7b400 exynos/snow: set SPI clock rate in romstage main

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 0f7b400f2e3497cf37758f4b14040930bea22391
Author: David Hendricks <dhendrix at chromium.org>
Date:   Sat Feb 9 16:42:23 2013 -0800

    exynos/snow: set SPI clock rate in romstage main
    
    This moves the setting of SPI clock rate into romstage's main,
    which allows us to eliminate a bunch of dependencies from the
    bootblock (about 7KB worth).
    
    Change-Id: I371499bb4af6a6aa838294bc56f9dbc21864957a
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Reviewed-on: http://review.coreboot.org/2346
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Sun Feb 10 02:58:51 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Sun Feb 10 04:02:46 2013, giving +2
See http://review.coreboot.org/2346 for details.

-gerrit