[coreboot] building a coreboot (and 100% free software) compatible box

Rudolf Marek r.marek at assembler.cz
Thu Feb 7 10:52:16 CET 2013

>> 1) NB firmware - most likely needed for PCIe - never tried without

This is firmware inside coreboot AGESA (15tn), most likely it is some soft core 
CPU implemented in NB. Did not disassemble this yet.

>> 2) SB firmware - IMC - you dont need to load this

This is 8051 firmware, but most system have strap pin for IMC disabled athough 
you can enable it via software and run own programs there. I disassembled most 
of the firmware and I was even run own stuff there.

>> 3) XHCI - you dont need to load this - no USB3.0

This is in 3rd party blobs repository. No clue what CPU it has or what it does.

>> 4) CPU microcode - you will have problems if you don't load this (need to check)

This is part of AGESA. It is not a firmware per se, but just some modification 
to internal CPU structure (very limited to space) so you cannot probably build 
your own instructions. At least those seems to be crypto signed in latest AMD CPUs.

>> 5) ATOM tables - you can interpret them via kernel driver

This is part of VGA ROM bios. You dont need to run vga rombios, radeon driver in 
kernel can do GPU POST. But you would have to check if the bytecode does not 
break the in kernel interpreter.

>> 6) GPU firmware - no GPU and no modesetting

no clue about internal structure or purpose.

> Sounds just great. Any pointers where can I look into these?

> Are you aware of any viable designs to do this?

Not sure, most likely opencores OpenRISC, but no idea about performance. There 
may be some ASIC at the end in the future.


> Thanks:
> Csillag

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