[coreboot] [coreboot-gerrit] Patch set updated for coreboot: 26eaf9d Family14: Add support for solder-down DDR memory

Paul Menzel paulepanter at users.sourceforge.net
Mon Dec 16 00:52:14 CET 2013

Dear Dave,

Am Sonntag, den 15.12.2013, 09:27 -0700 schrieb Dave Frodin:
> I'm still planning on reading the SPD values from a text file in the
> mainboard directory.

that is the same way, the Google boards are currently doing it [1],
right? The SPD-hex-files in the board directory are listed in a
Makefile. Can you use the same mechanism for AMD boards instead of your
current library approach [5]?

This implementation was pushed with the Chromebook Butterfly without any
discussion or announcement, so the Google folks might be able to tell us
why they went this route.

I like Vladimir’s suggestion to put the SPD data into CBFS so it can
easily be tuned [3]. No idea, what the downsides are.

        Why have a config for this? It would make more sense to look for
        a file and if it's there use it, otherwise go for smbus. This
        way you patch is also useful for oveclockers and boot-time

Do you also have the mainboard patch somewhere to look at, so the whole
picture is clear how the current patch is used?



PS: It would be awesome if you could avoid TOP posting and use
interleaved style [3].

[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/mainboard/samsung/lumpy/spd.hex;h=869088620789dfe35a0f0917d2441843d2503a95;hb=4f0e61eabe3d03662687f53d9167dd9c790f7e5c
[2] http://review.coreboot.org/2359
[3] http://review.coreboot.org/#/c/4532/3/src/northbridge/amd/agesa/family14/dimmSpd.c
[4] http://en.opensuse.org/openSUSE:Mailing_list_netiquette
[5] http://review.coreboot.org/4533
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