[coreboot] INTEL FSP support coreboot-v4.0-4966

Marc Jones marcj303 at gmail.com
Fri Dec 13 01:56:40 CET 2013

Hi Zoran,

On Thu, Dec 5, 2013 at 7:44 AM, Stojsavljevic, Zoran <
zoran.stojsavljevic at intel.com> wrote:

> Hello,
> I just noticed new patches/drops into Coreboot (Cougar Canyon 2 board
> added). I did take git snapshot, and tried to see few things (what was
> added there). Talking about snapshot v4.0-4966 .
> It seems that Emerald Lake 2 (EL2) and Cougar Canyon 2  (CC2) support two
> slightly different concepts. I switched from EL2 to CC2 (since I have EL2
> and CC2 here in lab, but only tried EL2 board with CC2 FSP context).

Thanks for the report. Yes EL2 uses a mrc/systemagent binary contributed by
Google. CC2 uses the FSP from Intel (and Sage). The FSP is new and we are
still working on making the coreboot side of the interface better.

> I needed to have 10+ adaptation building for CC2, and in this process I
> noticed the following:
> [1] CC2 has several parameters hard coded (in <chipset>);
Like? Send a patch.

> [2] The new directory added: src/cpu/intel/fsp_model_206ax (there is
> already model_206ax);

 We would like to support both, but each binary has some different setup
requirements and assumptions.

[3] This directory is out of sync (does not compile), so I added IVB
> microcode patches files (microcode_m2xxx_000000yy.h) and modified
> microcode_blob.h file;
This should match the microcode the is available with the FSP. The date of
current/best/working microcode is always an issue.

> [4] Added vbios (latest 2170.dat);
> [5] Did not noticed Management Engine (new concept for all other non-INTEL
> embedded folks, which suddenly popped up from nowhere) addendum (path) for
> CC2, which EL2 does have;

This is a chipset dependency.  Even different versions of the chipset may
require it or not.

> [6] Did not see/find descriptor.bin definition file and path definition
> (should be included somewhere);
Comes witht he FSP and/or you need to genterate it.

> [7] Used standard seabios from git as payload.
> And, yes, the whole Coreboot-v4.0-4966 does correctly compile with native
> gcc (NO cross-compiler) on my Fedora 18+ (Fedora 20) VM on my SNB DT:
> coreboot.rom: 8192 kB, bootblocksize 864, romsize 8388608, offset 0x400000
> alignment: 64 bytes
> Name                           Offset     Type         Size
> cmos_layout.bin                0x400000   cmos_layout  1164
> pci8086,0166.rom               0x4004c0   optionrom    65536
> cpu_microcode_blob.bin         0x410500   microcode    32832
> fallback/romstage              0x4185c0   stage        31082
> fallback/coreboot_ram          0x41ff80   stage        75924
> fallback/payload               0x432880   payload      55177
> config                         0x440080   raw          4426
> pci8086,1502.rom               0x441200   raw          67584
> (empty)                        0x451a40   null         3335512
> fsp.bin                        0x77ffc0   (unknown)    393216
> (empty)                        0x7e0000   null         130072
> Here is the question for thinking: both CC2 and EL2 choices should be
> unified, to reflect one steady procedure for INTEL  FSP, right?

We are trying to figure that out, but there are currently different
solutions for different needs.

> I sent this email not in negative connotation, just trying to understand
> how better to approach Coreboot configuration procedure. Since there are
> more than few paths to be selected and IDF tool to be used to generate
> descriptor.bin .

We are working on some documentation, and some also comes with the FSP.


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