[coreboot] PCI MMCONF on amdfam10
adurbin at chromium.org
Thu Dec 12 17:49:39 CET 2013
On Thu, Dec 12, 2013 at 7:02 AM, Kyösti Mälkki <kyosti.malkki at gmail.com> wrote:
> After commit 872c922 there is some trouble on PCI configuration access with
> Asus M4A785-M. This could apply to other amdfam10 too, although I have not
> yet received such reports.
> As the commit message stated, I had discovered that in the beginning of
> ramstage all PCI configuration access used the IO (0xcf8) method even though
> Kconfig specified MMCONF_SUPPORT_DEFAULT which should imply all PCI config
> access is done with MMCONF unless IO is explicitly requested.
> AFAICS, for all cores the MSR enabling MMCONF is programmed very early in
> the romstage. So second option for failure is there exists cases where IO
> must be used instead of MMCONF, but I could not find such documentation yet.
> I hope Dennis can reproduce the failure log and post it in the next few
Which devices weren't working? IIRC, on old AMD processors rev E and
maybe rev F the northbridge config space couldn't be accessed by
MMCONF -- only the cf8/cfc method.
More information about the coreboot