[coreboot] INTEL FSP support coreboot-v4.0-4966

Stojsavljevic, Zoran zoran.stojsavljevic at intel.com
Thu Dec 5 15:44:57 CET 2013


I just noticed new patches/drops into Coreboot (Cougar Canyon 2 board added). I did take git snapshot, and tried to see few things (what was added there). Talking about snapshot v4.0-4966 .

It seems that Emerald Lake 2 (EL2) and Cougar Canyon 2  (CC2) support two slightly different concepts. I switched from EL2 to CC2 (since I have EL2 and CC2 here in lab, but only tried EL2 board with CC2 FSP context).

I needed to have 10+ adaptation building for CC2, and in this process I noticed the following:
[1] CC2 has several parameters hard coded (in <chipset>);
[2] The new directory added: src/cpu/intel/fsp_model_206ax (there is already model_206ax);
[3] This directory is out of sync (does not compile), so I added IVB microcode patches files (microcode_m2xxx_000000yy.h) and modified microcode_blob.h file;
[4] Added vbios (latest 2170.dat);
[5] Did not noticed Management Engine (new concept for all other non-INTEL embedded folks, which suddenly popped up from nowhere) addendum (path) for CC2, which EL2 does have;
[6] Did not see/find descriptor.bin definition file and path definition (should be included somewhere);
[7] Used standard seabios from git as payload.

And, yes, the whole Coreboot-v4.0-4966 does correctly compile with native gcc (NO cross-compiler) on my Fedora 18+ (Fedora 20) VM on my SNB DT:

coreboot.rom: 8192 kB, bootblocksize 864, romsize 8388608, offset 0x400000
alignment: 64 bytes

Name                           Offset     Type         Size
cmos_layout.bin                0x400000   cmos_layout  1164
pci8086,0166.rom               0x4004c0   optionrom    65536
cpu_microcode_blob.bin         0x410500   microcode    32832
fallback/romstage              0x4185c0   stage        31082
fallback/coreboot_ram          0x41ff80   stage        75924
fallback/payload               0x432880   payload      55177
config                         0x440080   raw          4426
pci8086,1502.rom               0x441200   raw          67584
(empty)                        0x451a40   null         3335512
fsp.bin                        0x77ffc0   (unknown)    393216
(empty)                        0x7e0000   null         130072

Here is the question for thinking: both CC2 and EL2 choices should be unified, to reflect one steady procedure for INTEL  FSP, right?

I sent this email not in negative connotation, just trying to understand how better to approach Coreboot configuration procedure. Since there are more than few paths to be selected and IDF tool to be used to generate descriptor.bin .

Looking forward to some suggestions (from wide auditorium) to what I wrote here.

Thank you,

Intel GmbH
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