[coreboot] Ram initization

David Hendricks dhendrix at google.com
Mon Aug 26 21:47:56 CEST 2013

On Mon, Aug 26, 2013 at 1:13 AM, Patrick Georgi <patrick at georgi-clan.de>wrote:

> Am 26.08.2013 09:12, schrieb Mohit Gupta:
> > After that I get stuck completely mainly because of RAM initialization
> > steps as per JEDEC. I am looking for resources or tutorials which can
> > point to me in right direction as to how read SPD info and use that to
> > configure or initialize RAM module.
> Memory initialization varies a lot by the standard (DDR2 vs DDR3, for
> example), and - when looking at it from the point of view of a firmware
> implementer - also by the chipset that drives the memory. For example
> the VIA chipsets with DDR3 support seem to do many things by itself that
> must be handled explicitely by initialization code on other chipsets.
> I find our RAM init code for older Intel chipsets quite readable. But
> I'm probably biased because I was part of the development teams for that
> code.
> You can find it at src/northbridge/i945 (driving DDR2) and
> src/northbridge/gm45 (DDR3) in our source tree.
> http://www.coreboot.org/Git describes how to access the source code.

As Patrick pointed out, it is quite specific to the hardware you are
working on. And unfortunately documentation is scarce. Fortunately AMD
publishes a good deal of info about their DRAM controller init in their
BIOS and Kernel Developer's Guides (BKDG). Section 2.9.7 of the Family 16h
BKDG sheds some light on the steps involved:

In addition to the resources Patrick pointed out, you can also find DDR3
memory controller init code for Exynos5-series processors. The code for the
Exynos5420 currently lives in the coreboot repo on chromium.org and is not
too hairy:

David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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