[coreboot] [Coreboot ] LGA775 support

CTO of SPCTNC spctnc at gmail.com
Mon Apr 29 14:28:04 CEST 2013

How do you do.

Thank you for your effort for supporting coreboot.

I saw your patch to coreboot for LGA775 soket.


I 'm porting Coreboot to Gigabyte GA-945GCM board(LGA775 socket, i945GC

In my view, Coreboot does not support LGA775 perfectly.

Coreboot seems to have several problems with LGA775.

In my case, when it calls wbinvd on "smm_init"
function(southbridge/intel/i82801gx/smi.c: Line352),

, system goes away.


Here is the log:



PCI: 00:1f.3 cmd <- 101

PCI: 02:00.0 cmd <- 03


Initializing devices...

Root Device init


start_eip=0x00001000, code_size=0x00000031 




When the code calls wbinvd(), it stops. So, I skipped the calls of wbinvd()
or calls of disable_cache().

Then it go out more. But it also stops on [SMM-1].

Here is the log:



MTRR: Physical address space:

0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000007f800000 size 0x7f740000 type 6
0x000000007f800000 - 0x0000000100000000 size 0x80800000 type 0 call
enable_fixed_mtrr() CPU physical address size: 36 bits

MTRR: default type WB/UC MTRR counts: 2/2.

MTRR: UC selected as default type.

MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6

MTRR: 1 base 0x000000007f800000 mask 0x0000000fff800000 type 0


MTRR check

Fixed MTRRs   : Enabled

Variable MTRRs: Enabled


Setting up local apic... apic_id: 0x00 done.

CPU: 0 2 siblings

memalign Enter, boundary 8, size 152, free_mem_ptr 0015ac70 memalign

CPU: 0 has sibling 1

CPU #0 initialized

CPU1: stack_base 00158000, stack_end 00158ff8 Asserting INIT.

Waiting for send to finish...

+Deasserting INIT.

Waiting for send to finish...

+#startup loops: 2.

Sending STARTUP #1 to 1.

After apic_write.





Have you ever seen any board on which Coreboot works well?

If you have any idea, please contact me.


Thanks & regards.


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