[coreboot] New patch to review for coreboot: 18ae0cc Mainboard: Fix IO-HUB link number in Dinar mainboard

Aladyshev Konstantin (kostr@list.ru) gerrit at coreboot.org
Wed Sep 26 20:25:27 CEST 2012

Aladyshev Konstantin (kostr at list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1540


commit 18ae0cc9515987ce5725185f6b7f99fd0d9a3a2b
Author: Kostr <aladyshev at nicevt.ru>
Date:   Wed Sep 26 22:11:20 2012 +0400

    Mainboard: Fix IO-HUB link number in Dinar mainboard
    According to file "northbridge.c" in family 15h code
    IO-HUB should be placed on link_lsit[0] in devicetree.cb.
    This hack in "northbridge.c" was made to satisfy both f10 and f15 cpu's.
    Change-Id: I4754235bd38239460347b0dc4a82cd4e58ae7cd0
    Signed-off-by: Kostr <aladyshev at nicevt.ru>
 src/mainboard/amd/dinar/devicetree.cb | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb
index 92fe521..3211a2f 100644
--- a/src/mainboard/amd/dinar/devicetree.cb
+++ b/src/mainboard/amd/dinar/devicetree.cb
@@ -26,8 +26,7 @@ chip northbridge/amd/agesa/family15/root_complex
 	device pci_domain 0 on
 		subsystemid 0x1022 0x1705 inherit
 		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-			device pci 18.0 on end # Link 0
-			device pci 18.0 on     # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1)
+			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology to satisfy both f10 and f15 CPUs
 				chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex
 					device pci 0.0 on  end # HT Root Complex
 					device pci 0.1 off end # CLKCONFIG

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