[coreboot] Patch merged into coreboot/master: e23f859 inteltool: new definitions and cleanup

gerrit at coreboot.org gerrit at coreboot.org
Fri Oct 19 09:57:52 CEST 2012

the following patch was just integrated into master:
commit e23f859c861ae9f5e686485e76446e4beef2140b
Author: Stefan Tauner <stefan.tauner at gmx.at>
Date:   Sat Oct 13 02:19:30 2012 +0200

    inteltool: new definitions and cleanup
     - Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[].
     - Refine some names and macros.
     - Clean up some whitespace errors.
     - Add IDs and names of 5, 6 and 7 Series southbridges and the three
       latest Core CPU families with integrated memory controllers but do
       not implement any pretty printing routines for them yet.
       The first generation Core family is already supported, although it
       was wrongly named after the PCH and used the wrong ID. Also, the BAR
       values have been mangled to 32b instead of 64b. Both errors have been
       fixed and most basic support for the other two generations was added.
    Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95
    Signed-off-by: Stefan Tauner <stefan.tauner at gmx.at>

Build-Tested: build bot (Jenkins) at Sat Oct 13 02:40:52 2012, giving +1
Reviewed-By: Anton Kochkov <anton.kochkov at gmail.com> at Fri Oct 19 09:57:51 2012, giving +2
See http://review.coreboot.org/1574 for details.


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