[coreboot] New patch to review for coreboot: 83d20ce SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
Zheng Bao (zheng.bao@amd.com)
gerrit at coreboot.org
Tue Nov 27 08:33:30 CET 2012
Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1919
-gerrit
commit 83d20ce80f3a2ef306c837132e188d4acd072058
Author: Zheng Bao <fishbaozi at gmail.com>
Date: Tue Nov 27 16:52:41 2012 +0800
SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
For SST chips, The Write-Status-Register instruction must be
executed immediately after the execution of the
Enable-Write-Status-Register instruction, instead of Write-Enable.
Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Signed-off-by: zbao <fishbaozi at gmail.com>
---
src/drivers/spi/sst.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c
index 8245f72..ebeb441 100644
--- a/src/drivers/spi/sst.c
+++ b/src/drivers/spi/sst.c
@@ -20,6 +20,7 @@
#define CMD_SST_WRDI 0x04 /* Write Disable */
#define CMD_SST_RDSR 0x05 /* Read Status Register */
#define CMD_SST_WRSR 0x01 /* Write Status Register */
+#define CMD_SST_EWSR 0x50 /* Enable Write Status Register */
#define CMD_SST_READ 0x03 /* Read Data Bytes */
#define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_SST_BP 0x02 /* Byte Program */
@@ -101,6 +102,15 @@ sst_enable_writing(struct spi_flash *flash)
}
static int
+sst_enable_writing_status(struct spi_flash *flash)
+{
+ int ret = spi_flash_cmd(flash->spi, CMD_SST_EWSR, NULL, 0);
+ if (ret)
+ printk(BIOS_WARNING, "SF: Enabling Write Status failed\n");
+ return ret;
+}
+
+static int
sst_disable_writing(struct spi_flash *flash)
{
int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0);
@@ -212,7 +222,7 @@ sst_unlock(struct spi_flash *flash)
int ret;
u8 cmd, status;
- ret = sst_enable_writing(flash);
+ ret = sst_enable_writing_status(flash);
if (ret)
return ret;
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