[coreboot] New patch to review for coreboot: 7b92ec7 Add ddr3lv_support flag to pei_data structure

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1825

-gerrit

commit 7b92ec72dcbeab9797ce63503c9723556e0b6c4d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Jul 11 10:40:45 2012 -0700

    Add ddr3lv_support flag to pei_data structure
    
    This will enable DDR3 1.35V support for memory training in
    the reference code.  It requires the board to be setup for
    1.35V with whatever board-specific GPIOs are available.
    
    Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/northbridge/intel/sandybridge/pei_data.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index 34adddc..cabda3f 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -31,7 +31,7 @@
 #define PEI_DATA_H
 
 typedef void (*tx_byte_func)(unsigned char byte);
-#define PEI_VERSION 2
+#define PEI_VERSION 3
 struct pei_data
 {
 	uint32_t pei_version;
@@ -98,6 +98,7 @@ struct pei_data
 	 */
 	uint8_t spd_data[4][256];
 	tx_byte_func tx_byte;
+	int ddr3lv_support;
 } __attribute__((packed));
 
 #endif