[coreboot] Patch merged into coreboot/master: 2a700ec SPI: Configure Software Sequence SPI Freq to match descriptor

gerrit at coreboot.org gerrit at coreboot.org
Mon Nov 12 04:23:30 CET 2012

the following patch was just integrated into master:
commit 2a700ec16322561ad487e6ef1ae8878f9a7e4357
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Oct 8 15:26:54 2012 -0700

    SPI: Configure Software Sequence SPI Freq to match descriptor
    Right now the SPI bus is getting set to 20mhz for transactions
    initiated with the software sequence interface.
    In order to be able to do reasonable fastread/write/erase we
    can bump this up to a higher value at boot before it gets
    locked at 20mhz.
    To do this read out the speed set in the SPI descriptor for
    hardware sequencing and apply it to software sequencing.
    Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
    Reviewed-on: http://review.coreboot.org/1773
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Mon Nov 12 00:39:55 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Mon Nov 12 04:23:08 2012, giving +2
See http://review.coreboot.org/1773 for details.


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