[coreboot] Patch set updated for coreboot: 8159e7f SMM: Avoid use of global variables in SMI handler

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Fri Nov 9 01:55:35 CET 2012


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1764

-gerrit

commit 8159e7f8abad44cee620a9b2d6c1ec66718f0ac9
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Oct 3 19:01:57 2012 -0700

    SMM: Avoid use of global variables in SMI handler
    
    Using global variables with the TSEG is a bad idea because
    they are not relocated properly right now.  Instead make
    the variables static and add accessor functions for the
    rest of SMM to use.
    
    At the same time drop the tcg/smi1 pointers as they are
    not setup or ever used.  (the debug output is added back
    in a subsequent commit)
    
    Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/include/cpu/x86/smm.h                  |  3 +++
 src/southbridge/intel/bd82x6x/nvs.h        |  4 ++++
 src/southbridge/intel/bd82x6x/smihandler.c | 21 ++++++++++++---------
 3 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 82a5a1a..b52a315 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -384,4 +384,7 @@ u32 smi_get_tseg_base(void);
 void tseg_relocate(void **ptr);
 #endif
 
+/* Get PMBASE address */
+u16 smm_get_pmbase(void);
+
 #endif
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 2d94a64..385dc64 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -138,3 +138,7 @@ typedef struct {
 	chromeos_acpi_t chromeos;
 } __attribute__((packed)) global_nvs_t;
 
+#ifdef __SMM__
+/* Used in SMM to find the ACPI GNVS address */
+global_nvs_t *smm_get_gnvs(void);
+#endif
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index fb63030..3db2248 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -25,7 +25,6 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
 #include <device/pci_def.h>
 #include <cpu/x86/smm.h>
 #include <elog.h>
@@ -44,15 +43,22 @@
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
  */
-u16 pmbase = DEFAULT_PMBASE;
-u8 smm_initialized = 0;
+static u16 pmbase = DEFAULT_PMBASE;
+u16 smm_get_pmbase(void)
+{
+	return pmbase;
+}
+
+static u8 smm_initialized = 0;
 
 /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
  * by coreboot.
  */
-global_nvs_t *gnvs = (global_nvs_t *)0x0;
-void *tcg = (void *)0x0;
-void *smi1 = (void *)0x0;
+static global_nvs_t *gnvs = (global_nvs_t *)0x0;
+global_nvs_t *smm_get_gnvs(void)
+{
+	return gnvs;
+}
 
 #if CONFIG_SMM_TSEG
 static u32 tseg_base = 0;
@@ -521,10 +527,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 			return;
 		}
 		gnvs = *(global_nvs_t **)0x500;
-		tcg  = *(void **)0x504;
-		smi1 = *(void **)0x508;
 		smm_initialized = 1;
-		printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
 		break;
 #if CONFIG_ELOG_GSMI
 	case ELOG_GSMI_APM_CNT:




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