[coreboot] Patch set updated for coreboot: 7eb0a8f Define post codes for OS boot and resume
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Thu Nov 8 20:19:48 CET 2012
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1702
-gerrit
commit 7eb0a8f8b13c7214036a3ba28ccd444e7e9ea137
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Mon Aug 13 09:37:42 2012 -0700
Define post codes for OS boot and resume
And move the pre-hardwaremain post code to 0x79
so it comes before hardwaremain at 0x80.
Emit these codes from ACPI OS resume vector as well
as the finalize step in bd82x6x southbridge.
Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
src/arch/x86/boot/acpi.c | 1 +
src/include/console/post_codes.h | 21 +++++++++++++++++----
src/southbridge/intel/bd82x6x/finalize.c | 4 ++++
3 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index 72b6d96..ca2f1d4 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -630,6 +630,7 @@ void suspend_resume(void)
/* Call mainboard resume handler first, if defined. */
if (mainboard_suspend_resume)
mainboard_suspend_resume();
+ post_code(POST_OS_RESUME);
acpi_jump_to_wakeup(wake_vec);
}
}
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index c716b72..0cf7d6b 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -83,6 +83,13 @@
#define POST_ENTRY_C_START 0x13
/**
+ * \brief Pre call to hardwaremain()
+ *
+ * POSTed right before hardwaremain is called from c_start.S
+ */
+#define POST_PRE_HARDWAREMAIN 0x79
+
+/**
* \brief Entry into coreboot in hardwaremain (RAM)
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
@@ -166,12 +173,18 @@
#define POST_DEAD_CODE 0xee
/**
- * \brief Pre call to hardwaremain()
+ * \brief Final code before OS resumes
*
- * POSTed right before hardwaremain is called from c_start.S
- * TODO: Change this code to a lower number
+ * Called right before jumping to the OS resume vector.
+ */
+#define POST_OS_RESUME 0xfd
+
+/**
+ * \brief Final code before OS boots
+ *
+ * This may not be called depending on the payload used.
*/
-#define POST_PRE_HARDWAREMAIN 0xfe
+#define POST_OS_BOOT 0xfe
/**
* \brief Elfload fail or die() called
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index ed1ebf7..7bd9f3f 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -20,6 +20,7 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
+#include <console/post_codes.h>
#include <northbridge/intel/sandybridge/pcie_config.c>
#include "pch.h"
@@ -53,4 +54,7 @@ void intel_pch_finalize_smm(void)
RCBA32(0x21a4) = RCBA32(0x21a4);
pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+
+ /* Indicate finalize step with post code */
+ outb(POST_OS_BOOT, 0x80);
}
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