[coreboot] Patch merged into coreboot/master: becacec AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit becacec022602ae1ab876c58d8ae69092327b9fe
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date:   Wed Oct 31 15:39:51 2012 +0800

    AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU
    
    Each G34 socket has two node. Previous lapic algorithm is written for
    the CPU which has one node per socket. I test the code on h8qgi with
    4 family 15 CPUs(8 cores per CPU). The topology is:
    socket 0 --> Node 0, Node 1
    socket 2 --> Node 2, Node 3
    socket 1 --> Node 4, Node 5
    socket 3 --> Node 6, Node 7
    Each node has 4 cores.
    I change the code according to this topology.
    
    Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855
    Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
    Reviewed-on: http://review.coreboot.org/1659
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Tue Nov  6 16:17:14 2012, giving +1
See http://review.coreboot.org/1659 for details.

-gerrit