[coreboot] Patch set updated for coreboot: 422d1dc Tyan s8226: change lapic of lapic_cluster 0 to 0x30

Siyuan Wang (wangsiyuanbuaa@gmail.com) gerrit at coreboot.org
Tue Nov 6 15:53:10 CET 2012

Siyuan Wang (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1652


commit 422d1dcd6f7c4614a64d2e00548af7d7499a529b
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date:   Sun Oct 28 18:06:40 2012 +0800

    Tyan s8226: change lapic of lapic_cluster 0 to 0x30
    AMD family15 CPU has a lapic_cluster which is the same level with
    PCI domain. Now, the lapic is 0x20 which is already taken by CPU.
    There are two CPUs on s8226 and each CPU has 8 cores.
    CPU 0 takes lapic from 0x10 to 0x17 and CPU 1 takes from 0x20 to 0x27.
    Now, the dmesg complains as follow:
    do_IRQ: 1.55 No irq handler for vector (irq -1)
    I change lapic of lapic_cluster to 0x30.
    Although I am not sure what's the exactly meaning of lapic_cluster,
    this is a workaround to solve this issue.
    Change-Id: Ie17820e0f11d11c35e7e2351a454fa8e823bbf2c
    Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
 src/mainboard/tyan/s8226/devicetree.cb | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb
index 4459019..c7bd8c3 100644
--- a/src/mainboard/tyan/s8226/devicetree.cb
+++ b/src/mainboard/tyan/s8226/devicetree.cb
@@ -19,8 +19,7 @@
 chip northbridge/amd/agesa/family15/root_complex
 	device lapic_cluster 0 on
 		chip cpu/amd/agesa/family15
-			device lapic 0x20 on end #f15
-			#device lapic 0x10 on end #f10
+			device lapic 0x30 on end
 	device pci_domain 0 on

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